Add subtract and logical instruction encodings to Intel-32.

Also add versions with 8-bit and 32-bit immediate operands.

lib/cretonne/meta/isa/intel/encodings.py

@@ -4,10 +4,24 @@ Intel Encodings.
 from __future__ import absolute_import
 from base import instructions as base
 from .defs import I32
-from .recipes import Op1rr, Op1rc
+from .recipes import Op1rr, Op1rc, Op1rib, Op1rid
 from .recipes import OP
 
 I32.enc(base.iadd.i32, Op1rr, OP(0x01))
+I32.enc(base.isub.i32, Op1rr, OP(0x29))
+
+I32.enc(base.band.i32, Op1rr, OP(0x21))
+I32.enc(base.bor.i32, Op1rr, OP(0x09))
+I32.enc(base.bxor.i32, Op1rr, OP(0x31))
+
+# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
+for inst,                   r in [
+        (base.iadd_imm.i32, 0),
+        (base.band_imm.i32, 4),
+        (base.bor_imm.i32,  1),
+        (base.bxor_imm.i32, 6)]:
+    I32.enc(inst, Op1rib, OP(0x83, rrr=r))
+    I32.enc(inst, Op1rid, OP(0x81, rrr=r))
 
 # 32-bit shifts and rotates.
 # Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit

lib/cretonne/meta/isa/intel/recipes.py

@@ -3,8 +3,8 @@ Intel Encoding recipes.
 """
 from __future__ import absolute_import
 from cdsl.isa import EncRecipe
-# from cdsl.predicates import IsSignedInt
-from base.formats import Binary
+from cdsl.predicates import IsSignedInt
+from base.formats import Binary, BinaryImm
 from .registers import GPR
 
 # Opcode representation.
@@ -68,3 +68,13 @@ Op1rr = EncRecipe('Op1rr', Binary, size=2, ins=(GPR, GPR), outs=0)
 
 # XX /n with one arg in %rcx, for shifts.
 Op1rc = EncRecipe('Op1rc', Binary, size=2, ins=(GPR, GPR.rcx), outs=0)
+
+# XX /n ib with 8-bit immediate sign-extended.
+Op1rib = EncRecipe(
+        'Op1rib', BinaryImm, size=3, ins=GPR, outs=0,
+        instp=IsSignedInt(BinaryImm.imm, 8))
+
+# XX /n id with 32-bit immediate sign-extended.
+Op1rid = EncRecipe(
+        'Op1rid', BinaryImm, size=6, ins=GPR, outs=0,
+        instp=IsSignedInt(BinaryImm.imm, 32))

lib/cretonne/src/isa/intel/binemit.rs

@@ -53,3 +53,27 @@ fn recipe_op1rc<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut C
         panic!("Expected Binary format: {:?}", func.dfg[inst]);
     }
 }
+
+fn recipe_op1rib<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
+    if let InstructionData::BinaryImm { arg, imm, .. } = func.dfg[inst] {
+        let bits = func.encodings[inst].bits();
+        put_op1(bits, sink);
+        modrm_r_bits(func.locations[arg].unwrap_reg(), bits, sink);
+        let imm: i64 = imm.into();
+        sink.put1(imm as u8);
+    } else {
+        panic!("Expected BinaryImm format: {:?}", func.dfg[inst]);
+    }
+}
+
+fn recipe_op1rid<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
+    if let InstructionData::BinaryImm { arg, imm, .. } = func.dfg[inst] {
+        let bits = func.encodings[inst].bits();
+        put_op1(bits, sink);
+        modrm_r_bits(func.locations[arg].unwrap_reg(), bits, sink);
+        let imm: i64 = imm.into();
+        sink.put4(imm as u32);
+    } else {
+        panic!("Expected BinaryImm format: {:?}", func.dfg[inst]);
+    }
+}

lib/cretonne/src/isa/intel/enc_tables.rs

@@ -1,11 +1,12 @@
 //! Encoding tables for Intel ISAs.
 
-use ir::{Opcode, InstructionData};
 use ir::types;
+use ir::{Opcode, InstructionData};
 use isa::EncInfo;
 use isa::constraints::*;
 use isa::enc_tables::{Level1Entry, Level2Entry};
 use isa::encoding::RecipeSizing;
+use predicates;
 use super::registers::*;
 
 include!(concat!(env!("OUT_DIR"), "/encoding-intel.rs"));