Detailed debug-info (DWARF) support in new backends (initially x64).

This PR propagates "value labels" all the way from CLIF to DWARF
metadata on the emitted machine code. The key idea is as follows:

- Translate value-label metadata on the input into "value_label"
  pseudo-instructions when lowering into VCode. These
  pseudo-instructions take a register as input, denote a value label,
  and semantically are like a "move into value label" -- i.e., they
  update the current value (as seen by debugging tools) of the given
  local. These pseudo-instructions emit no machine code.

- Perform a dataflow analysis *at the machine-code level*, tracking
  value-labels that propagate into registers and into [SP+constant]
  stack storage. This is a forward dataflow fixpoint analysis where each
  storage location can contain a *set* of value labels, and each value
  label can reside in a *set* of storage locations. (Meet function is
  pairwise intersection by storage location.)

  This analysis traces value labels symbolically through loads and
  stores and reg-to-reg moves, so it will naturally handle spills and
  reloads without knowing anything special about them.

- When this analysis converges, we have, at each machine-code offset, a
  mapping from value labels to some number of storage locations; for
  each offset for each label, we choose the best location (prefer
  registers). Note that we can choose any location, as the symbolic
  dataflow analysis is sound and guarantees that the value at the
  value_label instruction propagates to all of the named locations.

- Then we can convert this mapping into a format that the DWARF
  generation code (wasmtime's debug crate) can use.

This PR also adds the new-backend variant to the gdb tests on CI.

cranelift/codegen/src/machinst/adapter.rs

@@ -10,6 +10,9 @@ use crate::settings::Flags;
 #[cfg(feature = "testing_hooks")]
 use crate::regalloc::RegDiversions;
 
+#[cfg(feature = "unwind")]
+use crate::isa::unwind::systemv::RegisterMappingError;
+
 use core::any::Any;
 use std::borrow::Cow;
 use std::fmt;
@@ -134,6 +137,11 @@ impl TargetIsa for TargetIsaAdapter {
         self.backend.create_systemv_cie()
     }
 
+    #[cfg(feature = "unwind")]
+    fn map_regalloc_reg_to_dwarf(&self, r: Reg) -> Result<u16, RegisterMappingError> {
+        self.backend.map_reg_to_dwarf(r)
+    }
+
     fn as_any(&self) -> &dyn Any {
         self as &dyn Any
     }

cranelift/codegen/src/machinst/debug.rs

@@ -0,0 +1,414 @@
+//! Debug info analysis: computes value-label ranges from value-label markers in
+//! generated VCode.
+//!
+//! We "reverse-engineer" debug info like this because it is far more reliable
+//! than generating it while emitting code and keeping it in sync.
+//!
+//! This works by (i) observing "value-label marker" instructions, which are
+//! semantically just an assignment from a register to a "value label" (which
+//! one can think of as another register; they represent, e.g., Wasm locals) at
+//! a certain point in the code, and (ii) observing loads and stores to the
+//! stack and register moves.
+//!
+//! We track, at every program point, the correspondence between each value
+//! label and *all* locations in which it resides. E.g., if it is stored to the
+//! stack, we remember that it is in both a register and the stack slot; but if
+//! the register is later overridden, then we have it just in the stack slot.
+//! This allows us to avoid false-positives observing loads/stores that we think
+//! are spillslots but really aren't.
+//!
+//! We do a standard forward dataflow analysis to compute this info.
+
+use crate::ir::ValueLabel;
+use crate::machinst::*;
+use crate::value_label::{LabelValueLoc, ValueLabelsRanges, ValueLocRange};
+use log::trace;
+use regalloc::{Reg, RegUsageCollector};
+use std::collections::{HashMap, HashSet, VecDeque};
+use std::hash::Hash;
+
+#[derive(Clone, Copy, Debug, PartialEq, Eq, Hash)]
+enum ValueLoc {
+    Reg(Reg),
+    /// Nominal-SP offset.
+    Stack(i64),
+}
+
+impl From<ValueLoc> for LabelValueLoc {
+    fn from(v: ValueLoc) -> Self {
+        match v {
+            ValueLoc::Reg(r) => LabelValueLoc::Reg(r),
+            ValueLoc::Stack(off) => LabelValueLoc::SPOffset(off),
+        }
+    }
+}
+
+impl ValueLoc {
+    fn is_reg(self) -> bool {
+        match self {
+            ValueLoc::Reg(_) => true,
+            _ => false,
+        }
+    }
+    fn is_stack(self) -> bool {
+        match self {
+            ValueLoc::Stack(_) => true,
+            _ => false,
+        }
+    }
+}
+
+/// Mappings at one program point.
+#[derive(Clone, Debug)]
+struct AnalysisInfo {
+    // nominal SP relative to real SP.
+    nominal_sp_offset: Option<i64>,
+    label_to_locs: HashMap<ValueLabel, HashSet<ValueLoc>>,
+    reg_to_label: HashMap<Reg, ValueLabel>,
+    stack_to_label: HashMap<i64, ValueLabel>,
+}
+
+fn get_inst_writes<M: MachInst>(m: &M) -> Vec<Reg> {
+    // TODO: expose this part of regalloc.rs's interface publicly.
+    let mut vecs = RegUsageCollector::get_empty_reg_vecs_test_framework_only(false);
+    let mut coll = RegUsageCollector::new(&mut vecs);
+    m.get_regs(&mut coll);
+    vecs.defs.extend(vecs.mods.into_iter());
+    vecs.defs
+}
+
+impl AnalysisInfo {
+    fn new() -> Self {
+        AnalysisInfo {
+            nominal_sp_offset: Some(0),
+            label_to_locs: HashMap::new(),
+            reg_to_label: HashMap::new(),
+            stack_to_label: HashMap::new(),
+        }
+    }
+
+    fn clear_label(&mut self, label: ValueLabel) {
+        if let Some(locs) = self.label_to_locs.remove(&label) {
+            for loc in locs {
+                match loc {
+                    ValueLoc::Reg(r) => {
+                        self.reg_to_label.remove(&r);
+                    }
+                    ValueLoc::Stack(off) => {
+                        self.stack_to_label.remove(&off);
+                    }
+                }
+            }
+        }
+    }
+    fn clear_reg(&mut self, reg: Reg) {
+        if let Some(label) = self.reg_to_label.remove(&reg) {
+            if let Some(locs) = self.label_to_locs.get_mut(&label) {
+                locs.remove(&ValueLoc::Reg(reg));
+            }
+        }
+    }
+    fn clear_stack_off(&mut self, off: i64) {
+        if let Some(label) = self.stack_to_label.remove(&off) {
+            if let Some(locs) = self.label_to_locs.get_mut(&label) {
+                locs.remove(&ValueLoc::Stack(off));
+            }
+        }
+    }
+    fn def_label_at_reg(&mut self, label: ValueLabel, reg: Reg) {
+        self.clear_label(label);
+        self.label_to_locs
+            .entry(label)
+            .or_insert_with(|| HashSet::new())
+            .insert(ValueLoc::Reg(reg));
+        self.reg_to_label.insert(reg, label);
+    }
+    fn store_reg(&mut self, reg: Reg, off: i64) {
+        self.clear_stack_off(off);
+        if let Some(label) = self.reg_to_label.get(&reg) {
+            if let Some(locs) = self.label_to_locs.get_mut(label) {
+                locs.insert(ValueLoc::Stack(off));
+            }
+            self.stack_to_label.insert(off, *label);
+        }
+    }
+    fn load_reg(&mut self, reg: Reg, off: i64) {
+        self.clear_reg(reg);
+        if let Some(&label) = self.stack_to_label.get(&off) {
+            if let Some(locs) = self.label_to_locs.get_mut(&label) {
+                locs.insert(ValueLoc::Reg(reg));
+            }
+            self.reg_to_label.insert(reg, label);
+        }
+    }
+    fn move_reg(&mut self, to: Reg, from: Reg) {
+        self.clear_reg(to);
+        if let Some(&label) = self.reg_to_label.get(&from) {
+            if let Some(locs) = self.label_to_locs.get_mut(&label) {
+                locs.insert(ValueLoc::Reg(to));
+            }
+            self.reg_to_label.insert(to, label);
+        }
+    }
+
+    fn step<M: MachInst>(&mut self, inst: &M) {
+        for write in get_inst_writes(inst) {
+            self.clear_reg(write);
+        }
+        if let Some((label, reg)) = inst.defines_value_label() {
+            self.def_label_at_reg(label, reg);
+        }
+        match inst.stack_op_info() {
+            Some(MachInstStackOpInfo::LoadNomSPOff(reg, offset)) => {
+                self.load_reg(reg, offset + self.nominal_sp_offset.unwrap());
+            }
+            Some(MachInstStackOpInfo::StoreNomSPOff(reg, offset)) => {
+                self.store_reg(reg, offset + self.nominal_sp_offset.unwrap());
+            }
+            Some(MachInstStackOpInfo::NomSPAdj(offset)) => {
+                if self.nominal_sp_offset.is_some() {
+                    self.nominal_sp_offset = Some(self.nominal_sp_offset.unwrap() + offset);
+                }
+            }
+            _ => {}
+        }
+        if let Some((to, from)) = inst.is_move() {
+            let to = to.to_reg();
+            self.move_reg(to, from);
+        }
+    }
+}
+
+trait IntersectFrom {
+    fn intersect_from(&mut self, other: &Self) -> IntersectResult;
+}
+struct IntersectResult {
+    changed: bool,
+    remove: bool,
+}
+
+impl IntersectFrom for AnalysisInfo {
+    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
+        let mut changed = false;
+        changed |= self
+            .nominal_sp_offset
+            .intersect_from(&other.nominal_sp_offset)
+            .changed;
+        changed |= self
+            .label_to_locs
+            .intersect_from(&other.label_to_locs)
+            .changed;
+        changed |= self
+            .reg_to_label
+            .intersect_from(&other.reg_to_label)
+            .changed;
+        changed |= self
+            .stack_to_label
+            .intersect_from(&other.stack_to_label)
+            .changed;
+        IntersectResult {
+            changed,
+            remove: false,
+        }
+    }
+}
+
+impl<K, V> IntersectFrom for HashMap<K, V>
+where
+    K: Copy + Eq + Hash,
+    V: IntersectFrom,
+{
+    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
+        let mut changed = false;
+        let mut remove_keys = vec![];
+        for k in self.keys() {
+            if !other.contains_key(k) {
+                remove_keys.push(*k);
+            }
+        }
+        for k in remove_keys {
+            changed = true;
+            self.remove(&k);
+        }
+
+        let mut remove_keys = vec![];
+        for k in other.keys() {
+            if let Some(v) = self.get_mut(k) {
+                let result = v.intersect_from(other.get(k).unwrap());
+                changed |= result.changed;
+                if result.remove {
+                    remove_keys.push(*k);
+                }
+            }
+        }
+        for k in remove_keys {
+            changed = true;
+            self.remove(&k);
+        }
+
+        IntersectResult {
+            changed,
+            remove: self.len() == 0,
+        }
+    }
+}
+impl<T> IntersectFrom for HashSet<T>
+where
+    T: Copy + Eq + Hash,
+{
+    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
+        let mut changed = false;
+        let mut remove = vec![];
+        for val in self.iter() {
+            if !other.contains(val) {
+                remove.push(*val);
+            }
+        }
+        for val in remove {
+            changed = true;
+            self.remove(&val);
+        }
+
+        IntersectResult {
+            changed,
+            remove: self.len() == 0,
+        }
+    }
+}
+impl IntersectFrom for ValueLabel {
+    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
+        // Remove if not equal (simple top -> values -> bottom lattice)
+        IntersectResult {
+            changed: false,
+            remove: *self != *other,
+        }
+    }
+}
+impl<T> IntersectFrom for Option<T>
+where
+    T: Copy + Eq,
+{
+    fn intersect_from(&mut self, other: &Self) -> IntersectResult {
+        let mut changed = false;
+        if !(self.is_some() && other.is_some() && self == other) {
+            changed = true;
+            *self = None;
+        }
+        IntersectResult {
+            changed,
+            remove: self.is_none(),
+        }
+    }
+}
+
+pub(crate) fn compute<I: VCodeInst>(
+    insts: &[I],
+    inst_ends: &[u32],
+    label_insn_iix: &[u32],
+) -> ValueLabelsRanges {
+    let inst_start = |idx: usize| if idx == 0 { 0 } else { inst_ends[idx - 1] };
+
+    trace!("compute: insts =");
+    for i in 0..insts.len() {
+        trace!(" #{} end: {} -> {:?}", i, inst_ends[i], insts[i]);
+    }
+    trace!("label_insn_iix: {:?}", label_insn_iix);
+
+    // Info at each block head, indexed by label.
+    let mut block_starts: HashMap<u32, AnalysisInfo> = HashMap::new();
+
+    // Initialize state at entry.
+    block_starts.insert(0, AnalysisInfo::new());
+
+    // Worklist: basic-block start offset.
+    let mut worklist = VecDeque::new();
+    let mut worklist_set = HashSet::new();
+    worklist.push_back(0);
+    worklist_set.insert(0);
+
+    while !worklist.is_empty() {
+        let block = worklist.pop_front().unwrap();
+        worklist_set.remove(&block);
+
+        let mut state = block_starts.get(&block).unwrap().clone();
+        trace!("at block {} -> state: {:?}", block, state);
+        let mut iix = label_insn_iix[block as usize];
+        while iix < insts.len() as u32 {
+            state.step(&insts[iix as usize]);
+            trace!(" -> inst #{}: {:?}", iix, insts[iix as usize]);
+            trace!("    --> state: {:?}", state);
+
+            let term = insts[iix as usize].is_term();
+            if term.is_term() {
+                for succ in term.get_succs() {
+                    trace!("    SUCCESSOR block {}", succ.get());
+                    if let Some(succ_state) = block_starts.get_mut(&succ.get()) {
+                        trace!("       orig state: {:?}", succ_state);
+                        if succ_state.intersect_from(&state).changed {
+                            if worklist_set.insert(succ.get()) {
+                                worklist.push_back(succ.get());
+                            }
+                            trace!("        (changed)");
+                        }
+                        trace!("       new state: {:?}", succ_state);
+                    } else {
+                        // First time seeing this block
+                        block_starts.insert(succ.get(), state.clone());
+                        worklist.push_back(succ.get());
+                        worklist_set.insert(succ.get());
+                    }
+                }
+                break;
+            }
+
+            iix += 1;
+        }
+    }
+
+    // Now iterate over blocks one last time, collecting
+    // value-label locations.
+
+    let mut value_labels_ranges: ValueLabelsRanges = HashMap::new();
+    for block in 0..label_insn_iix.len() {
+        let start_iix = label_insn_iix[block];
+        let end_iix = if block == label_insn_iix.len() - 1 {
+            insts.len() as u32
+        } else {
+            label_insn_iix[block + 1]
+        };
+        let block = block as u32;
+        let mut state = block_starts.get(&block).unwrap().clone();
+        for iix in start_iix..end_iix {
+            let offset = inst_start(iix as usize);
+            let end = inst_ends[iix as usize];
+            state.step(&insts[iix as usize]);
+
+            for (label, locs) in &state.label_to_locs {
+                trace!("   inst {} has label {:?} -> locs {:?}", iix, label, locs);
+                // Find an appropriate loc: a register if possible, otherwise pick the first stack
+                // loc.
+                let reg = locs.iter().cloned().find(|l| l.is_reg());
+                let stack = locs.iter().cloned().find(|l| l.is_stack());
+                if let Some(loc) = reg.or(stack) {
+                    let loc = LabelValueLoc::from(loc);
+                    let list = value_labels_ranges.entry(*label).or_insert_with(|| vec![]);
+                    if list.is_empty()
+                        || list.last().unwrap().end <= offset
+                        || list.last().unwrap().loc != loc
+                    {
+                        list.push(ValueLocRange {
+                            loc,
+                            start: end,
+                            end: end + 1,
+                        });
+                    } else {
+                        list.last_mut().unwrap().end = end + 1;
+                    }
+                }
+            }
+        }
+    }
+
+    trace!("ret: {:?}", value_labels_ranges);
+    value_labels_ranges
+}

cranelift/codegen/src/machinst/lower.rs

@@ -13,6 +13,7 @@ use crate::ir::instructions::BranchInfo;
 use crate::ir::{
     ArgumentPurpose, Block, Constant, ConstantData, ExternalName, Function, GlobalValueData, Inst,
     InstructionData, MemFlags, Opcode, Signature, SourceLoc, Type, Value, ValueDef,
+    ValueLabelAssignments, ValueLabelStart,
 };
 use crate::machinst::{
     writable_value_regs, ABICallee, BlockIndex, BlockLoweringOrder, LoweredBlock, MachLabel, VCode,
@@ -24,7 +25,7 @@ use alloc::vec::Vec;
 use core::convert::TryInto;
 use log::debug;
 use regalloc::{Reg, StackmapRequestInfo, Writable};
-use smallvec::SmallVec;
+use smallvec::{smallvec, SmallVec};
 use std::fmt::Debug;
 
 /// An "instruction color" partitions CLIF instructions by side-effecting ops.
@@ -492,6 +493,14 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
     }
 
     fn gen_retval_setup(&mut self, gen_ret_inst: GenerateReturn) {
+        // Hack: to keep `vmctx` alive, if it exists, we emit a value label here
+        // for it if debug info is requested. This ensures that it exists either
+        // in a register or spillslot throughout the entire function body, and
+        // allows for a better debugging experience.
+        if let Some(vmctx_val) = self.f.special_param(ArgumentPurpose::VMContext) {
+            self.emit_value_label_marks_for_value(vmctx_val);
+        }
+
         let retval_regs = self.retval_regs.clone();
         for (i, regs) in retval_regs.into_iter().enumerate() {
             let regs = writable_value_regs(regs);
@@ -725,6 +734,9 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
             if has_side_effect || value_needed {
                 debug!("lowering: inst {}: {:?}", inst, self.f.dfg[inst]);
                 backend.lower(self, inst)?;
+                // Emit value-label markers if needed, to later recover debug
+                // mappings.
+                self.emit_value_label_markers_for_inst(inst);
             }
             if data.opcode().is_return() {
                 // Return: handle specially, using ABI-appropriate sequence.
@@ -744,6 +756,72 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
         Ok(())
     }
 
+    fn get_value_labels<'a>(&'a self, val: Value, depth: usize) -> Option<&'a [ValueLabelStart]> {
+        if let Some(ref values_labels) = self.f.dfg.values_labels {
+            debug!(
+                "get_value_labels: val {} -> {} -> {:?}",
+                val,
+                self.f.dfg.resolve_aliases(val),
+                values_labels.get(&self.f.dfg.resolve_aliases(val))
+            );
+            let val = self.f.dfg.resolve_aliases(val);
+            match values_labels.get(&val) {
+                Some(&ValueLabelAssignments::Starts(ref list)) => Some(&list[..]),
+                Some(&ValueLabelAssignments::Alias { value, .. }) if depth < 10 => {
+                    self.get_value_labels(value, depth + 1)
+                }
+                _ => None,
+            }
+        } else {
+            None
+        }
+    }
+
+    fn emit_value_label_marks_for_value(&mut self, val: Value) {
+        let mut markers: SmallVec<[I; 4]> = smallvec![];
+        let regs = self.value_regs[val];
+        if regs.len() > 1 {
+            return;
+        }
+        let reg = regs.only_reg().unwrap();
+
+        if let Some(label_starts) = self.get_value_labels(val, 0) {
+            let labels = label_starts
+                .iter()
+                .map(|&ValueLabelStart { label, .. }| label)
+                .collect::<FxHashSet<_>>();
+            for label in labels {
+                debug!(
+                    "value labeling: defines val {:?} -> reg {:?} -> label {:?}",
+                    val, reg, label,
+                );
+                markers.push(I::gen_value_label_marker(label, reg));
+            }
+        }
+        for marker in markers {
+            self.emit(marker);
+        }
+    }
+
+    fn emit_value_label_markers_for_inst(&mut self, inst: Inst) {
+        debug!(
+            "value labeling: srcloc {}: inst {}",
+            self.srcloc(inst),
+            inst
+        );
+        for &val in self.f.dfg.inst_results(inst) {
+            self.emit_value_label_marks_for_value(val);
+        }
+    }
+
+    fn emit_value_label_markers_for_block_args(&mut self, block: Block) {
+        debug!("value labeling: block {}", block);
+        for &arg in self.f.dfg.block_params(block) {
+            self.emit_value_label_marks_for_value(arg);
+        }
+        self.finish_ir_inst(SourceLoc::default());
+    }
+
     fn finish_ir_inst(&mut self, loc: SourceLoc) {
         // `bb_insts` is kept in reverse order, so emit the instructions in
         // reverse order.
@@ -885,6 +963,7 @@ impl<'func, I: VCodeInst> Lower<'func, I> {
             // Original block body.
             if let Some(bb) = lb.orig_block() {
                 self.lower_clif_block(backend, bb)?;
+                self.emit_value_label_markers_for_block_args(bb);
             }
             // In-edge phi moves.
             if let Some((pred, inst, succ)) = lb.in_edge() {

cranelift/codegen/src/machinst/mod.rs

@@ -52,45 +52,9 @@
 //!         |                        - all symbolic stack references to
 //!         |                          stackslots and spillslots are resolved
 //!         |                          to concrete FP-offset mem addresses.)
-//!         | [block/insn ordering]
 //!         |
-//!     VCode<arch_backend::Inst>   (machine instructions:
-//!         |                        - vcode.final_block_order is filled in.
-//!         |                        - new insn sequence from regalloc is
-//!         |                          placed back into vcode and block
-//!         |                          boundaries are updated.)
-//!         | [redundant branch/block
-//!         |  removal]
-//!         |
-//!     VCode<arch_backend::Inst>   (machine instructions:
-//!         |                        - all blocks that were just an
-//!         |                          unconditional branch are removed.)
-//!         |
-//!         | [branch finalization
-//!         |  (fallthroughs)]
-//!         |
-//!     VCode<arch_backend::Inst>   (machine instructions:
-//!         |                        - all branches are in lowered one-
-//!         |                          target form, but targets are still
-//!         |                          block indices.)
-//!         |
-//!         | [branch finalization
-//!         |  (offsets)]
-//!         |
-//!     VCode<arch_backend::Inst>   (machine instructions:
-//!         |                        - all branch offsets from start of
-//!         |                          function are known, and all branches
-//!         |                          have resolved-offset targets.)
-//!         |
-//!         | [MemArg finalization]
-//!         |
-//!     VCode<arch_backend::Inst>   (machine instructions:
-//!         |                        - all MemArg references to the constant
-//!         |                          pool are replaced with offsets.
-//!         |                        - all constant-pool data is collected
-//!         |                          in the VCode.)
-//!         |
-//!         | [binary emission]
+//!         | [binary emission via MachBuffer
+//!         |  with streaming branch resolution/simplification]
 //!         |
 //!     Vec<u8>                     (machine code!)
 //!
@@ -98,11 +62,11 @@
 
 use crate::binemit::{CodeInfo, CodeOffset, StackMap};
 use crate::ir::condcodes::IntCC;
-use crate::ir::{Function, SourceLoc, Type};
+use crate::ir::{Function, SourceLoc, Type, ValueLabel};
 use crate::isa::unwind::input as unwind_input;
 use crate::result::CodegenResult;
 use crate::settings::Flags;
-
+use crate::value_label::ValueLabelsRanges;
 use alloc::boxed::Box;
 use alloc::vec::Vec;
 use core::fmt::Debug;
@@ -111,10 +75,13 @@ use regalloc::RegUsageCollector;
 use regalloc::{
     RealReg, RealRegUniverse, Reg, RegClass, RegUsageMapper, SpillSlot, VirtualReg, Writable,
 };
-use smallvec::SmallVec;
+use smallvec::{smallvec, SmallVec};
 use std::string::String;
 use target_lexicon::Triple;
 
+#[cfg(feature = "unwind")]
+use crate::isa::unwind::systemv::RegisterMappingError;
+
 pub mod lower;
 pub use lower::*;
 pub mod vcode;
@@ -137,6 +104,7 @@ pub mod inst_common;
 pub use inst_common::*;
 pub mod valueregs;
 pub use valueregs::*;
+pub mod debug;
 
 /// A machine instruction.
 pub trait MachInst: Clone + Debug {
@@ -163,6 +131,11 @@ pub trait MachInst: Clone + Debug {
         true
     }
 
+    /// If this is a load or store to the stack, return that info.
+    fn stack_op_info(&self) -> Option<MachInstStackOpInfo> {
+        None
+    }
+
     /// Generate a move.
     fn gen_move(to_reg: Writable<Reg>, from_reg: Reg, ty: Type) -> Self;
 
@@ -223,6 +196,17 @@ pub trait MachInst: Clone + Debug {
     /// be dependent on compilation flags.
     fn ref_type_regclass(_flags: &Flags) -> RegClass;
 
+    /// Does this instruction define a ValueLabel? Returns the `Reg` whose value
+    /// becomes the new value of the `ValueLabel` after this instruction.
+    fn defines_value_label(&self) -> Option<(ValueLabel, Reg)> {
+        None
+    }
+
+    /// Create a marker instruction that defines a value label.
+    fn gen_value_label_marker(_label: ValueLabel, _reg: Reg) -> Self {
+        Self::gen_nop(0)
+    }
+
     /// A label-use kind: a type that describes the types of label references that
     /// can occur in an instruction.
     type LabelUse: MachInstLabelUse;
@@ -285,6 +269,35 @@ pub enum MachTerminator<'a> {
     Indirect(&'a [MachLabel]),
 }
 
+impl<'a> MachTerminator<'a> {
+    /// Get the successor labels named in a `MachTerminator`.
+    pub fn get_succs(&self) -> SmallVec<[MachLabel; 2]> {
+        let mut ret = smallvec![];
+        match self {
+            &MachTerminator::Uncond(l) => {
+                ret.push(l);
+            }
+            &MachTerminator::Cond(l1, l2) => {
+                ret.push(l1);
+                ret.push(l2);
+            }
+            &MachTerminator::Indirect(ls) => {
+                ret.extend(ls.iter().cloned());
+            }
+            _ => {}
+        }
+        ret
+    }
+
+    /// Is this a terminator?
+    pub fn is_term(&self) -> bool {
+        match self {
+            MachTerminator::None => false,
+            _ => true,
+        }
+    }
+}
+
 /// A trait describing the ability to encode a MachInst into binary machine code.
 pub trait MachInstEmit: MachInst {
     /// Persistent state carried across `emit` invocations.
@@ -330,6 +343,8 @@ pub struct MachCompileResult {
     pub disasm: Option<String>,
     /// Unwind info.
     pub unwind_info: Option<unwind_input::UnwindInfo<Reg>>,
+    /// Debug info: value labels to registers/stackslots at code offsets.
+    pub value_labels_ranges: Option<ValueLabelsRanges>,
 }
 
 impl MachCompileResult {
@@ -386,13 +401,17 @@ pub trait MachBackend {
         Ok(None)
     }
 
-    /// Machine-specific condcode info needed by TargetIsa.
     /// Creates a new System V Common Information Entry for the ISA.
     #[cfg(feature = "unwind")]
     fn create_systemv_cie(&self) -> Option<gimli::write::CommonInformationEntry> {
         // By default, an ISA cannot create a System V CIE
         None
     }
+    /// Maps a regalloc::Reg to a DWARF register number.
+    #[cfg(feature = "unwind")]
+    fn map_reg_to_dwarf(&self, _: Reg) -> Result<u16, RegisterMappingError> {
+        Err(RegisterMappingError::UnsupportedArchitecture)
+    }
 }
 
 /// Expected unwind info type.
@@ -431,3 +450,15 @@ pub trait UnwindInfoGenerator<I: MachInstEmit> {
         context: UnwindInfoContext<I>,
     ) -> CodegenResult<Option<unwind_input::UnwindInfo<Reg>>>;
 }
+
+/// Info about an operation that loads or stores from/to the stack.
+#[derive(Clone, Copy, Debug)]
+pub enum MachInstStackOpInfo {
+    /// Load from an offset from the nominal stack pointer into the given reg.
+    LoadNomSPOff(Reg, i64),
+    /// Store to an offset from the nominal stack pointer from the given reg.
+    StoreNomSPOff(Reg, i64),
+    /// Adjustment of nominal-SP up or down. This value is added to subsequent
+    /// offsets in loads/stores above to produce real-SP offsets.
+    NomSPAdj(i64),
+}

cranelift/codegen/src/machinst/vcode.rs

@@ -21,7 +21,6 @@ use crate::ir::{self, types, Constant, ConstantData, SourceLoc};
 use crate::machinst::*;
 use crate::settings;
 use crate::timing;
-
 use regalloc::Function as RegallocFunction;
 use regalloc::Set as RegallocSet;
 use regalloc::{
@@ -110,8 +109,12 @@ pub struct VCode<I: VCodeInst> {
     /// Ranges for prologue and epilogue instructions.
     prologue_epilogue_ranges: Option<(InsnRange, Box<[InsnRange]>)>,
 
-    /// Instruction end offsets
-    insts_layout: RefCell<(Vec<u32>, u32)>,
+    /// Do we generate debug info?
+    generate_debug_info: bool,
+
+    /// Instruction end offsets, instruction indices at each label, and total
+    /// buffer size.  Only present if `generate_debug_info` is set.
+    insts_layout: RefCell<(Vec<u32>, Vec<u32>, u32)>,
 
     /// Constants.
     constants: VCodeConstants,
@@ -157,7 +160,13 @@ impl<I: VCodeInst> VCodeBuilder<I> {
         constants: VCodeConstants,
     ) -> VCodeBuilder<I> {
         let reftype_class = I::ref_type_regclass(abi.flags());
-        let vcode = VCode::new(abi, emit_info, block_order, constants);
+        let vcode = VCode::new(
+            abi,
+            emit_info,
+            block_order,
+            constants,
+            /* generate_debug_info = */ true,
+        );
         let stack_map_info = StackmapRequestInfo {
             reftype_class,
             reftyped_vregs: vec![],
@@ -296,6 +305,7 @@ impl<I: VCodeInst> VCode<I> {
         emit_info: I::Info,
         block_order: BlockLoweringOrder,
         constants: VCodeConstants,
+        generate_debug_info: bool,
     ) -> VCode<I> {
         VCode {
             liveins: abi.liveins(),
@@ -314,7 +324,8 @@ impl<I: VCodeInst> VCode<I> {
             safepoint_insns: vec![],
             safepoint_slots: vec![],
             prologue_epilogue_ranges: None,
-            insts_layout: RefCell::new((vec![], 0)),
+            generate_debug_info,
+            insts_layout: RefCell::new((vec![], vec![], 0)),
             constants,
         }
     }
@@ -484,7 +495,8 @@ impl<I: VCodeInst> VCode<I> {
         buffer.reserve_labels_for_blocks(self.num_blocks() as BlockIndex);
         buffer.reserve_labels_for_constants(&self.constants);
 
-        let mut insts_layout = vec![0; self.insts.len()];
+        let mut inst_ends = vec![0; self.insts.len()];
+        let mut label_insn_iix = vec![0; self.num_blocks()];
 
         let mut safepoint_idx = 0;
         let mut cur_srcloc = None;
@@ -500,6 +512,7 @@ impl<I: VCodeInst> VCode<I> {
 
             let (start, end) = self.block_ranges[block as usize];
             buffer.bind_label(MachLabel::from_block(block));
+            label_insn_iix[block as usize] = start;
             for iix in start..end {
                 let srcloc = self.srclocs[iix as usize];
                 if cur_srcloc != Some(srcloc) {
@@ -526,7 +539,19 @@ impl<I: VCodeInst> VCode<I> {
 
                 self.insts[iix as usize].emit(&mut buffer, &self.emit_info, &mut state);
 
-                insts_layout[iix as usize] = buffer.cur_offset();
+                if self.generate_debug_info {
+                    // Buffer truncation may have happened since last inst append; trim inst-end
+                    // layout info as appropriate.
+                    let l = &mut inst_ends[0..iix as usize];
+                    for end in l.iter_mut().rev() {
+                        if *end > buffer.cur_offset() {
+                            *end = buffer.cur_offset();
+                        } else {
+                            break;
+                        }
+                    }
+                    inst_ends[iix as usize] = buffer.cur_offset();
+                }
             }
 
             if cur_srcloc.is_some() {
@@ -553,7 +578,16 @@ impl<I: VCodeInst> VCode<I> {
             buffer.defer_constant(label, data.alignment(), data.as_slice(), u32::max_value());
         }
 
-        *self.insts_layout.borrow_mut() = (insts_layout, buffer.cur_offset());
+        if self.generate_debug_info {
+            for end in inst_ends.iter_mut().rev() {
+                if *end > buffer.cur_offset() {
+                    *end = buffer.cur_offset();
+                } else {
+                    break;
+                }
+            }
+            *self.insts_layout.borrow_mut() = (inst_ends, label_insn_iix, buffer.cur_offset());
+        }
 
         buffer
     }
@@ -567,13 +601,23 @@ impl<I: VCodeInst> VCode<I> {
         let context = UnwindInfoContext {
             insts: &self.insts,
             insts_layout: &layout.0,
-            len: layout.1,
+            len: layout.2,
             prologue: prologue.clone(),
             epilogues,
         };
         I::UnwindInfo::create_unwind_info(context)
     }
 
+    /// Generates value-label ranges.
+    pub fn value_labels_ranges(&self) -> crate::result::CodegenResult<Option<ValueLabelsRanges>> {
+        let layout = &self.insts_layout.borrow();
+        Ok(Some(debug::compute(
+            &self.insts,
+            &layout.0[..],
+            &layout.1[..],
+        )))
+    }
+
     /// Get the IR block for a BlockIndex, if one exists.
     pub fn bindex_to_bb(&self, block: BlockIndex) -> Option<ir::Block> {
         self.block_order.lowered_order()[block as usize].orig_block()