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Cranelift: don't emit inside lowering rules for aarch64 (#4572)

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* Cranelift: Don't `emit` inside lowering rules in aarch64

The lowering rules should be "pure" and side-effect free, using helpers defined
in `inst.isle` to perform actual side effects like emitting instructions.

* Cranelift: use 80 width for section separators in aarch64 lowering rules
This commit is contained in:
Nick Fitzgerald
2022-08-01 16:43:42 -07:00
committed by GitHub
parent fb59de15af
commit c77bec4dcb
2 changed files with 16 additions and 8 deletions
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10
cranelift/codegen/src/isa/aarch64/inst.isle
View File

@@ -1905,6 +1905,16 @@
(decl uqxtn2 (Reg Reg ScalarSize) Reg) (decl uqxtn2 (Reg Reg ScalarSize) Reg)
(rule (uqxtn2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Uqxtn) x y size)) (rule (uqxtn2 x y size) (vec_rr_narrow_high (VecRRNarrowOp.Uqxtn) x y size))
;; Helper for generating `fence` instructions.
(decl aarch64_fence () SideEffectNoResult)
(rule (aarch64_fence)
(SideEffectNoResult.Inst (MInst.Fence)))
;; Helper for generating `brk` instructions.
(decl brk () SideEffectNoResult)
(rule (brk)
(SideEffectNoResult.Inst (MInst.Brk)))
;; Helper for generating `addp` instructions. ;; Helper for generating `addp` instructions.
(decl addp (Reg Reg VectorSize) Reg) (decl addp (Reg Reg VectorSize) Reg)
(rule (addp x y size) (vec_rrr (VecALUOp.Addp) x y size)) (rule (addp x y size) (vec_rrr (VecALUOp.Addp) x y size))

14
cranelift/codegen/src/isa/aarch64/lower.isle
View File

@@ -1700,28 +1700,26 @@
(result Reg (uqxtn2 low_half y (lane_size ty)))) (result Reg (uqxtn2 low_half y (lane_size ty))))
result)) result))
;;;; Rules for `Fence` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `Fence` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (fence)) (rule (lower (fence))
(let ((_ Unit (emit (MInst.Fence)))) (side_effect (aarch64_fence)))
(output_none)))
;;;; Rules for `IsNull` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `IsNull` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type out_ty (is_null x @ (value_type ty)))) (rule (lower (has_type out_ty (is_null x @ (value_type ty))))
(with_flags (cmp_imm (operand_size ty) x (u8_into_imm12 0)) (with_flags (cmp_imm (operand_size ty) x (u8_into_imm12 0))
(materialize_bool_result (materialize_bool_result
(ty_bits out_ty) (Cond.Eq)))) (ty_bits out_ty) (Cond.Eq))))
;;;; Rules for `IsInvalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `IsInvalid` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type out_ty (is_invalid x @ (value_type ty)))) (rule (lower (has_type out_ty (is_invalid x @ (value_type ty))))
(with_flags (cmn_imm (operand_size ty) x (u8_into_imm12 1)) (with_flags (cmn_imm (operand_size ty) x (u8_into_imm12 1))
(materialize_bool_result (materialize_bool_result
(ty_bits out_ty) (Cond.Eq)))) (ty_bits out_ty) (Cond.Eq))))
;;;; Rules for `Debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `Debugtrap` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (debugtrap)) (rule (lower (debugtrap))
(let ((_ Unit (emit (MInst.Brk)))) (side_effect (brk)))
(output_none)))