machinst: allow passing constant information to the instruction emitter;

A new associated type Info is added to MachInstEmit, which is the
immutable counterpart to State. It can't easily be constructed from an
ABICallee, since it would require adding an associated type to the
latter, and making so leaks the associated type in a lot of places in
the code base and makes the code harder to read. Instead, the EmitInfo
state can simply be passed to the `Vcode::emit` function directly.

cranelift/codegen/src/isa/arm32/inst/emit.rs

@@ -255,10 +255,27 @@ impl EmitState {
     }
 }
 
+pub struct EmitInfo {
+    flags: settings::Flags,
+}
+
+impl EmitInfo {
+    pub(crate) fn new(flags: settings::Flags) -> Self {
+        EmitInfo { flags }
+    }
+}
+
+impl MachInstEmitInfo for EmitInfo {
+    fn flags(&self) -> &settings::Flags {
+        &self.flags
+    }
+}
+
 impl MachInstEmit for Inst {
+    type Info = EmitInfo;
     type State = EmitState;
 
-    fn emit(&self, sink: &mut MachBuffer<Inst>, flags: &settings::Flags, state: &mut EmitState) {
+    fn emit(&self, sink: &mut MachBuffer<Inst>, emit_info: &Self::Info, state: &mut EmitState) {
         let start_off = sink.cur_offset();
 
         match self {
@@ -446,7 +463,7 @@ impl MachInstEmit for Inst {
             } => {
                 let (mem_insts, mem) = mem_finalize(mem, state);
                 for inst in mem_insts.into_iter() {
-                    inst.emit(sink, flags, state);
+                    inst.emit(sink, emit_info, state);
                 }
                 if let Some(srcloc) = srcloc {
                     // Register the offset at which the store instruction starts.
@@ -484,7 +501,7 @@ impl MachInstEmit for Inst {
             } => {
                 let (mem_insts, mem) = mem_finalize(mem, state);
                 for inst in mem_insts.into_iter() {
-                    inst.emit(sink, flags, state);
+                    inst.emit(sink, emit_info, state);
                 }
                 if let Some(srcloc) = srcloc {
                     // Register the offset at which the load instruction starts.
@@ -537,7 +554,7 @@ impl MachInstEmit for Inst {
             &Inst::LoadAddr { rd, ref mem } => {
                 let (mem_insts, mem) = mem_finalize(mem, state);
                 for inst in mem_insts.into_iter() {
-                    inst.emit(sink, flags, state);
+                    inst.emit(sink, emit_info, state);
                 }
                 let inst = match mem {
                     AMode::RegReg(reg1, reg2, shift) => {
@@ -574,7 +591,7 @@ impl MachInstEmit for Inst {
                     }
                     _ => unreachable!(),
                 };
-                inst.emit(sink, flags, state);
+                inst.emit(sink, emit_info, state);
             }
             &Inst::Extend {
                 rd,
@@ -617,7 +634,7 @@ impl MachInstEmit for Inst {
                     rn: rm,
                     imm8: UImm8::maybe_from_i64(1).unwrap(),
                 };
-                inst.emit(sink, flags, state);
+                inst.emit(sink, emit_info, state);
 
                 if signed {
                     let inst = Inst::AluRRImm8 {
@@ -626,7 +643,7 @@ impl MachInstEmit for Inst {
                         rn: rd.to_reg(),
                         imm8: UImm8::maybe_from_i64(1).unwrap(),
                     };
-                    inst.emit(sink, flags, state);
+                    inst.emit(sink, emit_info, state);
                 }
             }
             &Inst::Extend { .. } => {
@@ -638,7 +655,7 @@ impl MachInstEmit for Inst {
 
                 sink.put2(enc_16_it(cond, insts));
                 for inst in insts.iter() {
-                    inst.inst.emit(sink, flags, state);
+                    inst.inst.emit(sink, emit_info, state);
                 }
             }
             &Inst::Push { ref reg_list } => match reg_list.len() {
@@ -703,7 +720,7 @@ impl MachInstEmit for Inst {
                 // continue:
                 //
                 if start_off & 0x3 != 0 {
-                    Inst::Nop2.emit(sink, flags, state);
+                    Inst::Nop2.emit(sink, emit_info, state);
                 }
                 assert_eq!(sink.cur_offset() & 0x3, 0);
 
@@ -715,12 +732,12 @@ impl MachInstEmit for Inst {
                     bits: 32,
                     sign_extend: false,
                 };
-                inst.emit(sink, flags, state);
+                inst.emit(sink, emit_info, state);
 
                 let inst = Inst::Jump {
                     dest: BranchTarget::ResolvedOffset(4),
                 };
-                inst.emit(sink, flags, state);
+                inst.emit(sink, emit_info, state);
 
                 sink.add_reloc(srcloc, Reloc::Abs4, name, offset.into());
                 sink.put4(0);
@@ -779,7 +796,7 @@ impl MachInstEmit for Inst {
                 emit_32(enc_32_cond_branch(cond, dest), sink);
 
                 let trap = Inst::Udf { trap_info };
-                trap.emit(sink, flags, state);
+                trap.emit(sink, emit_info, state);
             }
             &Inst::VirtualSPOffsetAdj { offset } => {
                 debug!(

cranelift/codegen/src/isa/arm32/mod.rs

@@ -17,7 +17,7 @@ mod inst;
 mod lower;
 mod lower_inst;
 
-use inst::create_reg_universe;
+use inst::{create_reg_universe, EmitInfo};
 
 /// An ARM32 backend.
 pub struct Arm32Backend {
@@ -44,8 +44,9 @@ impl Arm32Backend {
     ) -> CodegenResult<VCode<inst::Inst>> {
         // This performs lowering to VCode, register-allocates the code, computes
         // block layout and finalizes branches. The result is ready for binary emission.
+        let emit_info = EmitInfo::new(flags.clone());
         let abi = Box::new(abi::Arm32ABICallee::new(func, flags)?);
-        compile::compile::<Arm32Backend>(func, self, abi)
+        compile::compile::<Arm32Backend>(func, self, abi, emit_info)
     }
 }