T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Tidy up whitespace.

Browse Source
This commit is contained in:
Dan Gohman
2018-03-04 22:37:34 -08:00
parent 0ea0146e58
commit c59e9180de
12 changed files with 33 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
lib/cretonne/meta/base/instructions.py
View File

@@ -1699,7 +1699,7 @@ fpromote = Instruction(
This is an exact operation.
Cretonne currently only supports two floating point formats
- :type:`f32` and :type:`f64`. This may change in the future.
- :type:`f32` and :type:`f64`. This may change in the future.
The result type must have the same number of vector lanes as the input,
and the result lanes must not have fewer bits than the input lanes. If
@@ -1715,10 +1715,10 @@ fdemote = Instruction(
by rounding to nearest, ties to even.
Cretonne currently only supports two floating point formats
- :type:`f32` and :type:`f64`. This may change in the future.
- :type:`f32` and :type:`f64`. This may change in the future.
The result type must have the same number of vector lanes as the input,
and the result lanes must not have more bits than the input lanes. If
and the result lanes must not have more bits than the input lanes. If
the input and output types are the same, this is a no-op.
""",
ins=x, outs=a, constraints=WiderOrEq(Float, FloatTo))

2
lib/cretonne/meta/cdsl/test_ti.py
View File

@@ -96,7 +96,7 @@ def check_concrete_typing_rtl(var_types, rtl):
# type: (VarTyping, Rtl) -> None
"""
Check that a concrete type assignment var_types (Dict[Var, TypeVar]) is
valid for an Rtl rtl. Specifically check that:
valid for an Rtl rtl. Specifically check that:
1) For each Var v \in rtl, v is defined in var_types

12
lib/cretonne/meta/cdsl/ti.py
View File

@@ -322,7 +322,7 @@ class TypeEnv(object):
# type: (TypeVar, TypeVar) -> None
"""
Record a that the free tv1 is part of the same equivalence class as
tv2. The canonical representative of the merged class is tv2's
tv2. The canonical representative of the merged class is tv2's
cannonical representative.
"""
assert not tv1.is_derived
@@ -364,9 +364,9 @@ class TypeEnv(object):
# type: (TypeVar) -> int
"""
Get the rank of tv in the partial order. TVs directly associated with a
Var get their rank from the Var (see register()). Internally generated
Var get their rank from the Var (see register()). Internally generated
non-derived TVs implicitly get the lowest rank (0). Derived variables
get their rank from their free typevar. Singletons have the highest
get their rank from their free typevar. Singletons have the highest
rank. TVs associated with vars in a source pattern have a higher rank
than TVs associted with temporary vars.
"""
@@ -381,7 +381,7 @@ class TypeEnv(object):
def register(self, v):
# type: (Var) -> None
"""
Register a new Var v. This computes a rank for the associated TypeVar
Register a new Var v. This computes a rank for the associated TypeVar
for v, which is used to impose a partial order on type variables.
"""
self.vars.add(v)
@@ -848,7 +848,7 @@ def ti_def(definition, typ):
def ti_rtl(rtl, typ):
# type: (Rtl, TypeEnv) -> TypingOrError
"""
Perform type inference on an Rtl in a starting type env typ. Return an
Perform type inference on an Rtl in a starting type env typ. Return an
updated type environment or error.
"""
for (i, d) in enumerate(rtl.rtl):
@@ -866,7 +866,7 @@ def ti_rtl(rtl, typ):
def ti_xform(xform, typ):
# type: (XForm, TypeEnv) -> TypingOrError
"""
Perform type inference on an Rtl in a starting type env typ. Return an
Perform type inference on an Rtl in a starting type env typ. Return an
updated type environment or error.
"""
typ_or_err = ti_rtl(xform.src, typ)

4
lib/cretonne/meta/cdsl/xform.py
View File

@@ -113,8 +113,8 @@ class Rtl(object):
# type: (Rtl) -> None
"""
Given that there is only 1 possible concrete typing T for self, assign
a singleton TV with type t=T[v] for each Var v \in self. Its an error
to call this on an Rtl with more than 1 possible typing. This modifies
a singleton TV with type t=T[v] for each Var v \in self. Its an error
to call this on an Rtl with more than 1 possible typing. This modifies
the Rtl in-place.
"""
from .ti import ti_rtl, TypeEnv

2
lib/cretonne/meta/gen_legalizer.py
View File

@@ -211,7 +211,7 @@ def unwrap_inst(iref, node, fmt):
fmt.format('let typeof_{0} = pos.func.dfg.value_type({0});', v)
# If the node has results, detach the values.
# Place the values in locals.
# Place the values in locals.
replace_inst = False
if len(node.defs) > 0:
if node.defs == node.defs[0].dst_def.defs:

4
lib/cretonne/meta/isa/intel/instructions.py
View File

@@ -154,7 +154,7 @@ rflags = Operand('rflags', iflags)
bsr = Instruction(
'x86_bsr', r"""
Bit Scan Reverse -- returns the bit-index of the most significant 1
in the word. Result is undefined if the argument is zero. However, it
in the word. Result is undefined if the argument is zero. However, it
sets the Z flag depending on the argument, so it is at least easy to
detect and handle that case.
@@ -166,7 +166,7 @@ bsr = Instruction(
bsf = Instruction(
'x86_bsf', r"""
Bit Scan Forwards -- returns the bit-index of the least significant 1
in the word. Is otherwise identical to 'bsr', just above.
in the word. Is otherwise identical to 'bsr', just above.
""",
ins=x, outs=(y, rflags))

2
lib/cretonne/meta/semantics/__init__.py
View File

@@ -17,7 +17,7 @@ def verify_semantics(inst, src, xforms):
# type: (Instruction, Rtl, InstructionSemantics) -> None
"""
Verify that the semantics transforms in xforms correctly describe the
instruction described by the src Rtl. This involves checking that:
instruction described by the src Rtl. This involves checking that:
0) src is a single instance of inst
1) For all x\in xforms x.src is a single instance of inst
2) For any concrete values V of Literals in inst: