Enable the ssa verifier in debug builds (#5354)
Enable regalloc2's SSA verifier in debug builds to check for any outstanding reuse of virtual registers in def constraints. As fuzzing enables debug_assertions, this will enable the SSA verifier when fuzzing as well.
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@@ -57,6 +57,11 @@ pub fn compile<B: LowerBackend + TargetIsa>(
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let _tt = timing::regalloc();
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let mut options = RegallocOptions::default();
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options.verbose_log = b.flags().regalloc_verbose_logs();
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if cfg!(debug_assertions) {
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options.validate_ssa = true;
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}
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regalloc2::run(&vcode, machine_env, &options)
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.map_err(|err| {
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log::error!(
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@@ -100,6 +100,9 @@ pub trait MachInst: Clone + Debug {
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/// (ret/uncond/cond) and target if applicable.
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fn is_term(&self) -> MachTerminator;
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/// Is this an unconditional trap?
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fn is_trap(&self) -> bool;
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/// Is this an "args" pseudoinst?
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fn is_args(&self) -> bool;
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@@ -1220,6 +1220,12 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
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}
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fn block_params(&self, block: BlockIndex) -> &[VReg] {
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// As a special case we don't return block params for the entry block, as all the arguments
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// will be defined by the `Inst::Args` instruction.
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if block == self.entry {
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return &[];
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}
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let (start, end) = self.block_params_range[block.index()];
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let ret = &self.block_params[start as usize..end as usize];
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// Currently block params are never aliased to another vreg, but
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@@ -1239,6 +1245,8 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
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fn is_ret(&self, insn: InsnIndex) -> bool {
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match self.insts[insn.index()].is_term() {
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// We treat blocks terminated by an unconditional trap like a return for regalloc.
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MachTerminator::None => self.insts[insn.index()].is_trap(),
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MachTerminator::Ret => true,
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_ => false,
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}
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