Enable the ssa verifier in debug builds (#5354)

Enable regalloc2's SSA verifier in debug builds to check for any outstanding reuse of virtual registers in def constraints. As fuzzing enables debug_assertions, this will enable the SSA verifier when fuzzing as well.
This commit is contained in:
Trevor Elliott
2022-12-07 12:22:51 -08:00
committed by GitHub
parent f0c4b6f3a1
commit c5379051c4
22 changed files with 304 additions and 254 deletions

View File

@@ -57,6 +57,11 @@ pub fn compile<B: LowerBackend + TargetIsa>(
let _tt = timing::regalloc();
let mut options = RegallocOptions::default();
options.verbose_log = b.flags().regalloc_verbose_logs();
if cfg!(debug_assertions) {
options.validate_ssa = true;
}
regalloc2::run(&vcode, machine_env, &options)
.map_err(|err| {
log::error!(

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@@ -100,6 +100,9 @@ pub trait MachInst: Clone + Debug {
/// (ret/uncond/cond) and target if applicable.
fn is_term(&self) -> MachTerminator;
/// Is this an unconditional trap?
fn is_trap(&self) -> bool;
/// Is this an "args" pseudoinst?
fn is_args(&self) -> bool;

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@@ -1220,6 +1220,12 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
}
fn block_params(&self, block: BlockIndex) -> &[VReg] {
// As a special case we don't return block params for the entry block, as all the arguments
// will be defined by the `Inst::Args` instruction.
if block == self.entry {
return &[];
}
let (start, end) = self.block_params_range[block.index()];
let ret = &self.block_params[start as usize..end as usize];
// Currently block params are never aliased to another vreg, but
@@ -1239,6 +1245,8 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
fn is_ret(&self, insn: InsnIndex) -> bool {
match self.insts[insn.index()].is_term() {
// We treat blocks terminated by an unconditional trap like a return for regalloc.
MachTerminator::None => self.insts[insn.index()].is_trap(),
MachTerminator::Ret => true,
_ => false,
}