Format with nightly rustfmt-preview, then with rustfmt-0.9 again.

cranelift/src/cat.rs

@@ -3,8 +3,8 @@
 //! Read a sequence of Cretonne IR files and print them again to stdout. This has the effect of
 //! normalizing formatting and removing comments.
 
-use cton_reader::parse_functions;
 use CommandResult;
+use cton_reader::parse_functions;
 use utils::read_to_string;
 
 pub fn run(files: &[String]) -> CommandResult {

cranelift/src/compile.rs

@@ -1,12 +1,12 @@
 //! CLI tool to read Cretonne IR files and compile them into native code.
 
-use cton_reader::parse_test;
-use std::path::PathBuf;
 use cretonne::Context;
+use cretonne::print_errors::pretty_error;
 use cretonne::settings::FlagsOrIsa;
 use cretonne::{binemit, ir};
-use cretonne::print_errors::pretty_error;
+use cton_reader::parse_test;
 use std::path::Path;
+use std::path::PathBuf;
 use utils::{parse_sets_and_isa, read_to_string};
 
 struct PrintRelocs {

cranelift/src/cton-util.rs

@@ -14,12 +14,12 @@ use docopt::Docopt;
 use std::io::{self, Write};
 use std::process;
 
-mod utils;
 mod cat;
+mod compile;
 mod print_cfg;
 mod rsfilecheck;
+mod utils;
 mod wasm;
-mod compile;
 
 const USAGE: &str = "
 Cretonne code generator utility

cranelift/src/rsfilecheck.rs

@@ -3,9 +3,9 @@
 //! This file is named to avoid a name collision with the filecheck crate.
 
 use CommandResult;
-use utils::read_to_string;
 use filecheck::{Checker, CheckerBuilder, NO_VARIABLES};
 use std::io::{self, Read};
+use utils::read_to_string;
 
 pub fn run(files: &[String], verbose: bool) -> CommandResult {
     if files.is_empty() {

cranelift/src/utils.rs

@@ -1,8 +1,8 @@
 //! Utility functions.
 
+use cretonne::isa;
 use cretonne::isa::TargetIsa;
 use cretonne::settings::{self, FlagsOrIsa};
-use cretonne::isa;
 use cton_reader::{parse_options, Location};
 use std::fs::File;
 use std::io::{self, Read};

cranelift/src/wasm.rs

@@ -3,15 +3,15 @@
 //! Reads Wasm binary files, translates the functions' code to Cretonne IR.
 #![cfg_attr(feature = "cargo-clippy", allow(too_many_arguments, cyclomatic_complexity))]
 
-use cton_wasm::{translate_module, DummyEnvironment, ModuleEnvironment};
-use std::path::PathBuf;
 use cretonne::Context;
-use cretonne::settings::FlagsOrIsa;
 use cretonne::print_errors::{pretty_error, pretty_verifier_error};
-use std::fs::File;
+use cretonne::settings::FlagsOrIsa;
+use cton_wasm::{translate_module, DummyEnvironment, ModuleEnvironment};
 use std::error::Error;
+use std::fs::File;
 use std::io;
 use std::path::Path;
+use std::path::PathBuf;
 use std::process::Command;
 use tempdir::TempDir;
 use term;

lib/cretonne/src/abi.rs

@@ -186,8 +186,8 @@ pub fn legalize_abi_value(have: Type, arg: &AbiParam) -> ValueConversion {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use ir::types;
     use ir::AbiParam;
+    use ir::types;
 
     #[test]
     fn legalize() {

lib/cretonne/src/bforest/map.rs

@@ -1,8 +1,8 @@
 //! Forest of maps.
 
+use super::{Comparator, Forest, Node, NodeData, NodePool, Path, INNER_SIZE};
 use packed_option::PackedOption;
 use std::marker::PhantomData;
-use super::{Comparator, Forest, Node, NodeData, NodePool, Path, INNER_SIZE};
 
 /// Tag type defining forest types for a map.
 struct MapTypes<K, V, C>(PhantomData<(K, V, C)>);
@@ -422,10 +422,10 @@ where
 
 #[cfg(test)]
 mod test {
+    use super::super::NodeData;
+    use super::*;
     use std::mem;
     use std::vec::Vec;
-    use super::*;
-    use super::super::NodeData;
 
     #[test]
     fn node_size() {

lib/cretonne/src/bforest/node.rs

@@ -1,8 +1,8 @@
 //! B+-tree nodes.
 
+use super::{slice_insert, slice_shift, Forest, Node, SetValue, INNER_SIZE};
 use std::borrow::{Borrow, BorrowMut};
 use std::fmt;
-use super::{slice_insert, slice_shift, Forest, Node, SetValue, INNER_SIZE};
 
 /// B+-tree node.
 ///
@@ -579,9 +579,9 @@ where
 
 #[cfg(test)]
 mod test {
+    use super::*;
     use std::mem;
     use std::string::ToString;
-    use super::*;
 
     // Forest impl for a set implementation.
     struct TF();

lib/cretonne/src/bforest/path.rs

@@ -1,9 +1,9 @@
 //! A path from the root of a B+-tree to a leaf node.
 
+use super::node::Removed;
+use super::{slice_insert, slice_shift, Comparator, Forest, Node, NodeData, NodePool, MAX_PATH};
 use std::borrow::Borrow;
 use std::marker::PhantomData;
-use super::{slice_insert, slice_shift, Comparator, Forest, Node, NodeData, NodePool, MAX_PATH};
-use super::node::Removed;
 
 #[cfg(test)]
 use std::fmt;
@@ -699,9 +699,9 @@ impl<F: Forest> fmt::Display for Path<F> {
 
 #[cfg(test)]
 mod test {
-    use std::cmp::Ordering;
-    use super::*;
     use super::super::{Forest, NodeData, NodePool};
+    use super::*;
+    use std::cmp::Ordering;
 
     struct TC();
 

lib/cretonne/src/bforest/pool.rs

@@ -1,8 +1,8 @@
 //! B+-tree node pool.
 
+use super::{Forest, Node, NodeData};
 use entity::PrimaryMap;
 use std::ops::{Index, IndexMut};
-use super::{Forest, Node, NodeData};
 
 /// A pool of nodes, including a free list.
 pub(super) struct NodePool<F: Forest> {
@@ -77,11 +77,11 @@ impl<F: Forest> NodePool<F> {
         NodeData<F>: ::std::fmt::Display,
         F::Key: ::std::fmt::Display,
     {
+        use super::Comparator;
+        use entity::SparseSet;
         use std::borrow::Borrow;
         use std::cmp::Ordering;
         use std::vec::Vec;
-        use super::Comparator;
-        use entity::SparseSet;
 
         // The root node can't be an inner node with just a single sub-tree. It should have been
         // pruned.

lib/cretonne/src/bforest/set.rs

@@ -1,8 +1,8 @@
 //! Forest of sets.
 
+use super::{Comparator, Forest, Node, NodeData, NodePool, Path, SetValue, INNER_SIZE};
 use packed_option::PackedOption;
 use std::marker::PhantomData;
-use super::{Comparator, Forest, Node, NodeData, NodePool, Path, SetValue, INNER_SIZE};
 
 /// Tag type defining forest types for a set.
 struct SetTypes<K, C>(PhantomData<(K, C)>);
@@ -350,10 +350,10 @@ where
 
 #[cfg(test)]
 mod test {
+    use super::super::NodeData;
+    use super::*;
     use std::mem;
     use std::vec::Vec;
-    use super::*;
-    use super::super::NodeData;
 
     #[test]
     fn node_size() {

lib/cretonne/src/binemit/memorysink.rs

@@ -14,8 +14,8 @@
 //! relocations to a `RelocSink` trait object. Relocations are less frequent than the
 //! `CodeSink::put*` methods, so the performance impact of the virtual callbacks is less severe.
 
-use ir::{ExternalName, JumpTable, SourceLoc, TrapCode};
 use super::{Addend, CodeOffset, CodeSink, Reloc};
+use ir::{ExternalName, JumpTable, SourceLoc, TrapCode};
 use std::ptr::write_unaligned;
 
 /// A `CodeSink` that writes binary machine code directly into memory.

lib/cretonne/src/binemit/mod.rs

@@ -3,12 +3,12 @@
 //! The `binemit` module contains code for translating Cretonne's intermediate representation into
 //! binary machine code.
 
-mod relaxation;
 mod memorysink;
+mod relaxation;
 
-pub use regalloc::RegDiversions;
-pub use self::relaxation::relax_branches;
 pub use self::memorysink::{MemoryCodeSink, RelocSink, TrapSink};
+pub use self::relaxation::relax_branches;
+pub use regalloc::RegDiversions;
 
 use ir::{ExternalName, Function, Inst, JumpTable, SourceLoc, TrapCode};
 use std::fmt;

lib/cretonne/src/bitset.rs

@@ -5,9 +5,9 @@
 //!
 //! If you would like to add support for larger bitsets in the future, you need to change the trait
 //! bound Into<u32> and the u32 in the implementation of `max_bits()`.
+use std::convert::{From, Into};
 use std::mem::size_of;
 use std::ops::{Add, BitOr, Shl, Sub};
-use std::convert::{From, Into};
 
 /// A small bitset built on a single primitive integer type
 #[derive(Clone, Copy, Debug, PartialEq, Eq)]

lib/cretonne/src/context.rs

@@ -10,23 +10,23 @@
 //! single ISA instance.
 
 use binemit::{relax_branches, CodeOffset, MemoryCodeSink, RelocSink, TrapSink};
+use dce::do_dce;
 use dominator_tree::DominatorTree;
 use flowgraph::ControlFlowGraph;
 use ir::Function;
-use loop_analysis::LoopAnalysis;
 use isa::TargetIsa;
 use legalize_function;
+use licm::do_licm;
+use loop_analysis::LoopAnalysis;
+use postopt::do_postopt;
+use preopt::do_preopt;
 use regalloc;
 use result::{CtonError, CtonResult};
 use settings::{FlagsOrIsa, OptLevel};
+use simple_gvn::do_simple_gvn;
+use timing;
 use unreachable_code::eliminate_unreachable_code;
 use verifier;
-use dce::do_dce;
-use simple_gvn::do_simple_gvn;
-use licm::do_licm;
-use preopt::do_preopt;
-use postopt::do_postopt;
-use timing;
 
 /// Persistent data structures and compilation pipeline.
 pub struct Context {

lib/cretonne/src/dbg.rs

@@ -8,7 +8,6 @@
 ///
 /// The output will appear in files named `cretonne.dbg.*`, where the suffix is named after the
 /// thread doing the logging.
-
 use std::cell::RefCell;
 use std::env;
 use std::ffi::OsStr;

lib/cretonne/src/dce.rs

@@ -6,10 +6,10 @@
 use cursor::{Cursor, FuncCursor};
 use dominator_tree::DominatorTree;
 use entity::EntityRef;
-use ir::{DataFlowGraph, Function, Inst, Opcode};
 use ir::instructions::InstructionData;
-use timing;
+use ir::{DataFlowGraph, Function, Inst, Opcode};
 use std::vec::Vec;
+use timing;
 
 /// Test whether the given opcode is unsafe to even consider for DCE.
 fn trivially_unsafe_for_dce(opcode: Opcode) -> bool {

lib/cretonne/src/divconst_magic_numbers.rs

@@ -220,8 +220,8 @@ pub fn magicS64(d: i64) -> MS64 {
 
 #[cfg(test)]
 mod tests {
-    use super::{magicS32, magicS64, magicU32, magicU64};
     use super::{MS32, MS64, MU32, MU64};
+    use super::{magicS32, magicS64, magicU32, magicU64};
 
     fn mkMU32(mulBy: u32, doAdd: bool, shiftBy: i32) -> MU32 {
         MU32 {

lib/cretonne/src/dominator_tree.rs

@@ -2,14 +2,14 @@
 
 use entity::EntityMap;
 use flowgraph::{BasicBlock, ControlFlowGraph};
-use ir::{Ebb, ExpandedProgramPoint, Function, Inst, Layout, ProgramOrder, Value};
 use ir::instructions::BranchInfo;
+use ir::{Ebb, ExpandedProgramPoint, Function, Inst, Layout, ProgramOrder, Value};
 use packed_option::PackedOption;
 use std::cmp;
-use std::mem;
-use timing;
 use std::cmp::Ordering;
+use std::mem;
 use std::vec::Vec;
+use timing;
 
 /// RPO numbers are not first assigned in a contiguous way but as multiples of STRIDE, to leave
 /// room for modifications of the dominator tree.
@@ -666,12 +666,12 @@ impl DominatorTreePreorder {
 
 #[cfg(test)]
 mod test {
+    use super::*;
     use cursor::{Cursor, FuncCursor};
     use flowgraph::ControlFlowGraph;
     use ir::types::*;
     use ir::{Function, InstBuilder, TrapCode};
     use settings;
-    use super::*;
     use verifier::verify_context;
 
     #[test]

lib/cretonne/src/entity/list.rs

@@ -481,8 +481,8 @@ impl<T: EntityRef> EntityList<T> {
 mod tests {
     use super::*;
     use super::{sclass_for_length, sclass_size};
-    use ir::Inst;
     use entity::EntityRef;
+    use ir::Inst;
 
     #[test]
     fn size_classes() {

lib/cretonne/src/entity/map.rs

@@ -3,8 +3,8 @@
 use entity::{EntityRef, Iter, IterMut, Keys};
 use std::marker::PhantomData;
 use std::ops::{Index, IndexMut};
-use std::vec::Vec;
 use std::slice;
+use std::vec::Vec;
 
 /// A mapping `K -> V` for densely indexed entity references.
 ///

lib/cretonne/src/entity/mod.rs

@@ -29,16 +29,16 @@
 //!   references allocated from an associated memory pool. It has a much smaller footprint than
 //!   `Vec`.
 
-mod keys;
 mod iter;
+mod keys;
 mod list;
 mod map;
 mod primary;
-mod sparse;
 mod set;
+mod sparse;
 
-pub use self::keys::Keys;
 pub use self::iter::{Iter, IterMut};
+pub use self::keys::Keys;
 pub use self::list::{EntityList, ListPool};
 pub use self::map::EntityMap;
 pub use self::primary::PrimaryMap;
@@ -95,5 +95,5 @@ macro_rules! entity_impl {
                 (self as &::std::fmt::Display).fmt(f)
             }
         }
-    }
+    };
 }

lib/cretonne/src/entity/primary.rs

@@ -2,8 +2,8 @@
 use entity::{EntityRef, Iter, IterMut, Keys};
 use std::marker::PhantomData;
 use std::ops::{Index, IndexMut};
-use std::vec::Vec;
 use std::slice;
+use std::vec::Vec;
 
 /// A primary mapping `K -> V` allocating dense entity references.
 ///

lib/cretonne/src/flowgraph.rs

@@ -24,9 +24,9 @@
 //! and `(Ebb0, jmp Ebb2)` respectively.
 
 use bforest;
-use ir::{Ebb, Function, Inst};
-use ir::instructions::BranchInfo;
 use entity::EntityMap;
+use ir::instructions::BranchInfo;
+use ir::{Ebb, Function, Inst};
 use std::mem;
 use timing;
 

lib/cretonne/src/ir/builder.rs

@@ -216,9 +216,9 @@ impl<'f> InstBuilderBase<'f> for ReplaceBuilder<'f> {
 #[cfg(test)]
 mod tests {
     use cursor::{Cursor, FuncCursor};
-    use ir::{Function, InstBuilder, ValueDef};
-    use ir::types::*;
     use ir::condcodes::*;
+    use ir::types::*;
+    use ir::{Function, InstBuilder, ValueDef};
 
     #[test]
     fn types() {

lib/cretonne/src/ir/dfg.rs

@@ -1,20 +1,20 @@
 //! Data flow graph tracking Instructions, Values, and EBBs.
 
 use entity::{EntityMap, PrimaryMap};
-use isa::{Encoding, Legalize, TargetIsa};
 use ir;
 use ir::builder::ReplaceBuilder;
 use ir::extfunc::ExtFuncData;
 use ir::instructions::{BranchInfo, CallInfo, InstructionData};
 use ir::types;
 use ir::{Ebb, FuncRef, Inst, SigRef, Signature, Type, Value, ValueList, ValueListPool};
+use isa::{Encoding, Legalize, TargetIsa};
 use packed_option::ReservedValue;
-use write::write_operands;
 use std::fmt;
 use std::iter;
 use std::mem;
 use std::ops::{Index, IndexMut};
 use std::u16;
+use write::write_operands;
 
 /// A data flow graph defines all instructions and extended basic blocks in a function as well as
 /// the data flow dependencies between them. The DFG also tracks values which can be either

lib/cretonne/src/ir/entities.rs

@@ -261,8 +261,8 @@ impl From<Heap> for AnyEntity {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use std::u32;
     use std::string::ToString;
+    use std::u32;
 
     #[test]
     fn value_with_number() {
@@ -275,8 +275,8 @@ mod tests {
 
     #[test]
     fn memory() {
-        use std::mem;
         use packed_option::PackedOption;
+        use std::mem;
         // This is the whole point of `PackedOption`.
         assert_eq!(
             mem::size_of::<Value>(),

lib/cretonne/src/ir/function.rs

@@ -7,9 +7,9 @@ use binemit::CodeOffset;
 use entity::{EntityMap, PrimaryMap};
 use ir;
 use ir::{CallConv, DataFlowGraph, ExternalName, Layout, Signature};
-use ir::{EbbOffsets, InstEncodings, JumpTables, SourceLocs, StackSlots, ValueLocations};
 use ir::{Ebb, ExtFuncData, FuncRef, GlobalVar, GlobalVarData, Heap, HeapData, JumpTable,
          JumpTableData, SigRef, StackSlot, StackSlotData};
+use ir::{EbbOffsets, InstEncodings, JumpTables, SourceLocs, StackSlots, ValueLocations};
 use isa::{EncInfo, Legalize, TargetIsa};
 use std::fmt;
 use write::write_function;

lib/cretonne/src/ir/globalvar.rs

@@ -1,7 +1,7 @@
 //! Global variables.
 
-use ir::{ExternalName, GlobalVar};
 use ir::immediates::Offset32;
+use ir::{ExternalName, GlobalVar};
 use std::fmt;
 
 /// Information about a global variable declaration.

lib/cretonne/src/ir/heap.rs

@@ -1,7 +1,7 @@
 //! Heaps.
 
-use ir::immediates::Imm64;
 use ir::GlobalVar;
+use ir::immediates::Imm64;
 use std::fmt;
 
 /// Information about a heap declaration.

lib/cretonne/src/ir/immediates.rs

@@ -651,10 +651,10 @@ impl FromStr for Ieee64 {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use std::{f32, f64};
-    use std::str::FromStr;
     use std::fmt::Display;
+    use std::str::FromStr;
     use std::string::ToString;
+    use std::{f32, f64};
 
     #[test]
     fn format_imm64() {

lib/cretonne/src/ir/instructions.rs

@@ -7,17 +7,17 @@
 //! directory.
 
 use std::fmt::{self, Display, Formatter};
-use std::str::FromStr;
 use std::ops::{Deref, DerefMut};
+use std::str::FromStr;
 use std::vec::Vec;
 
 use ir;
-use ir::{Ebb, FuncRef, JumpTable, SigRef, Type, Value};
 use ir::types;
+use ir::{Ebb, FuncRef, JumpTable, SigRef, Type, Value};
 use isa;
 
-use entity;
 use bitset::BitSet;
+use entity;
 use ref_slice::{ref_slice, ref_slice_mut};
 
 /// Some instructions use an external list of argument values because there is not enough space in

lib/cretonne/src/ir/jumptable.rs

@@ -3,11 +3,11 @@
 //! Jump tables are declared in the preamble and assigned an `ir::entities::JumpTable` reference.
 //! The actual table of destinations is stored in a `JumpTableData` struct defined in this module.
 
-use packed_option::PackedOption;
 use ir::entities::Ebb;
+use packed_option::PackedOption;
+use std::fmt::{self, Display, Formatter};
 use std::iter;
 use std::slice;
-use std::fmt::{self, Display, Formatter};
 use std::vec::Vec;
 
 /// Contents of a jump table.
@@ -140,10 +140,10 @@ impl Display for JumpTableData {
 #[cfg(test)]
 mod tests {
     use super::JumpTableData;
-    use ir::Ebb;
     use entity::EntityRef;
-    use std::vec::Vec;
+    use ir::Ebb;
     use std::string::ToString;
+    use std::vec::Vec;
 
     #[test]
     fn empty() {

lib/cretonne/src/ir/layout.rs

@@ -4,8 +4,8 @@
 //! determined by the `Layout` data structure defined in this module.
 
 use entity::EntityMap;
-use ir::{Ebb, Inst};
 use ir::progpoint::{ExpandedProgramPoint, ProgramOrder};
+use ir::{Ebb, Inst};
 use packed_option::PackedOption;
 use std::cmp;
 use std::iter::{IntoIterator, Iterator};
@@ -736,8 +736,8 @@ impl<'f> DoubleEndedIterator for Insts<'f> {
 
 #[cfg(test)]
 mod tests {
-    use cursor::{Cursor, CursorPosition};
     use super::Layout;
+    use cursor::{Cursor, CursorPosition};
     use entity::EntityRef;
     use ir::{Ebb, Inst, ProgramOrder, SourceLoc};
     use std::cmp::Ordering;

lib/cretonne/src/ir/mod.rs

@@ -1,25 +1,25 @@
 //! Representation of Cretonne IR functions.
 
-pub mod types;
-pub mod entities;
-pub mod condcodes;
-pub mod immediates;
-pub mod instructions;
-pub mod stackslot;
-pub mod jumptable;
-pub mod dfg;
-pub mod layout;
-pub mod function;
 mod builder;
+pub mod condcodes;
+pub mod dfg;
+pub mod entities;
 mod extfunc;
 mod extname;
+pub mod function;
 mod globalvar;
 mod heap;
+pub mod immediates;
+pub mod instructions;
+pub mod jumptable;
+pub mod layout;
 mod libcall;
 mod memflags;
 mod progpoint;
 mod sourceloc;
+pub mod stackslot;
 mod trapcode;
+pub mod types;
 mod valueloc;
 
 pub use ir::builder::{InsertBuilder, InstBuilder, InstBuilderBase, InstInserterBase};

lib/cretonne/src/ir/progpoint.rs

@@ -2,9 +2,9 @@
 
 use entity::EntityRef;
 use ir::{Ebb, Inst, ValueDef};
+use std::cmp;
 use std::fmt;
 use std::u32;
-use std::cmp;
 
 /// A `ProgramPoint` represents a position in a function where the live range of an SSA value can
 /// begin or end. It can be either:

lib/cretonne/src/ir/stackslot.rs

@@ -8,8 +8,8 @@ use ir::{StackSlot, Type};
 use packed_option::PackedOption;
 use std::cmp;
 use std::fmt;
-use std::slice;
 use std::ops::{Index, IndexMut};
+use std::slice;
 use std::str::FromStr;
 use std::vec::Vec;
 
@@ -338,9 +338,9 @@ impl StackSlots {
 
 #[cfg(test)]
 mod tests {
+    use super::*;
     use ir::Function;
     use ir::types;
-    use super::*;
     use std::string::ToString;
 
     #[test]

lib/cretonne/src/ir/valueloc.rs

@@ -3,8 +3,8 @@
 //! The register allocator assigns every SSA value to either a register or a stack slot. This
 //! assignment is represented by a `ValueLoc` object.
 
-use isa::{RegInfo, RegUnit};
 use ir::StackSlot;
+use isa::{RegInfo, RegUnit};
 use std::fmt;
 
 /// Value location.

lib/cretonne/src/isa/arm32/abi.rs

@@ -1,10 +1,10 @@
 //! ARM ABI implementation.
 
+use super::registers::{D, GPR, Q, S};
 use ir;
 use isa::RegClass;
 use regalloc::AllocatableSet;
 use settings as shared_settings;
-use super::registers::{D, GPR, Q, S};
 
 /// Legalize `sig`.
 pub fn legalize_signature(

lib/cretonne/src/isa/arm32/mod.rs

@@ -1,20 +1,20 @@
 //! ARM 32-bit Instruction Set Architecture.
 
-pub mod settings;
 mod abi;
 mod binemit;
 mod enc_tables;
 mod registers;
+pub mod settings;
 
-use binemit::{emit_function, CodeSink, MemoryCodeSink};
 use super::super::settings as shared_settings;
-use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
+use binemit::{emit_function, CodeSink, MemoryCodeSink};
-use isa::Builder as IsaBuilder;
-use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use ir;
+use isa::Builder as IsaBuilder;
+use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
+use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use regalloc;
-use std::fmt;
 use std::boxed::Box;
+use std::fmt;
 
 #[allow(dead_code)]
 struct Isa {

lib/cretonne/src/isa/arm64/abi.rs

@@ -1,10 +1,10 @@
 //! ARM 64 ABI implementation.
 
+use super::registers::{FPR, GPR};
 use ir;
 use isa::RegClass;
 use regalloc::AllocatableSet;
 use settings as shared_settings;
-use super::registers::{FPR, GPR};
 
 /// Legalize `sig`.
 pub fn legalize_signature(

lib/cretonne/src/isa/arm64/mod.rs

@@ -1,20 +1,20 @@
 //! ARM 64-bit Instruction Set Architecture.
 
-pub mod settings;
 mod abi;
 mod binemit;
 mod enc_tables;
 mod registers;
+pub mod settings;
 
-use binemit::{emit_function, CodeSink, MemoryCodeSink};
 use super::super::settings as shared_settings;
-use isa::enc_tables::{lookup_enclist, Encodings};
+use binemit::{emit_function, CodeSink, MemoryCodeSink};
-use isa::Builder as IsaBuilder;
-use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use ir;
+use isa::Builder as IsaBuilder;
+use isa::enc_tables::{lookup_enclist, Encodings};
+use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use regalloc;
-use std::fmt;
 use std::boxed::Box;
+use std::fmt;
 
 #[allow(dead_code)]
 struct Isa {

lib/cretonne/src/isa/constraints.rs

@@ -8,8 +8,8 @@
 //! are satisfied.
 
 use binemit::CodeOffset;
-use isa::{RegClass, RegUnit};
 use ir::{Function, Inst, ValueLoc};
+use isa::{RegClass, RegUnit};
 use regalloc::RegDiversions;
 
 /// Register constraint for a single value operand or instruction result.

lib/cretonne/src/isa/intel/abi.rs

@@ -1,18 +1,18 @@
 //! Intel ABI implementation.
 
-use ir;
-use isa::{RegClass, RegUnit, TargetIsa};
-use regalloc::AllocatableSet;
-use settings as shared_settings;
 use super::registers::{FPR, GPR, RU};
 use abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
-use ir::{AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, CallConv, InstBuilder};
+use cursor::{Cursor, CursorPosition, EncCursor};
-use ir::stackslot::{StackOffset, StackSize};
+use ir;
 use ir::immediates::Imm64;
+use ir::stackslot::{StackOffset, StackSize};
+use ir::{AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, CallConv, InstBuilder};
+use isa::{RegClass, RegUnit, TargetIsa};
+use regalloc::AllocatableSet;
+use result;
+use settings as shared_settings;
 use stack_layout::layout_stack;
 use std::i32;
-use cursor::{Cursor, CursorPosition, EncCursor};
-use result;
 
 /// Argument registers for x86-64
 static ARG_GPRS: [RU; 6] = [RU::rdi, RU::rsi, RU::rdx, RU::rcx, RU::r8, RU::r9];

lib/cretonne/src/isa/intel/binemit.rs

@@ -1,11 +1,11 @@
 //! Emitting binary Intel machine code.
 
+use super::registers::RU;
 use binemit::{bad_encoding, CodeSink, Reloc};
-use ir::{Ebb, Function, Inst, InstructionData, Opcode, TrapCode};
 use ir::condcodes::{CondCode, FloatCC, IntCC};
+use ir::{Ebb, Function, Inst, InstructionData, Opcode, TrapCode};
 use isa::{RegUnit, StackBase, StackBaseMask, StackRef};
 use regalloc::RegDiversions;
-use super::registers::RU;
 
 include!(concat!(env!("OUT_DIR"), "/binemit-intel.rs"));
 

lib/cretonne/src/isa/intel/enc_tables.rs

@@ -1,16 +1,16 @@
 //! Encoding tables for Intel ISAs.
 
+use super::registers::*;
 use bitset::BitSet;
 use cursor::{Cursor, FuncCursor};
 use flowgraph::ControlFlowGraph;
-use ir::{self, InstBuilder};
 use ir::condcodes::IntCC;
+use ir::{self, InstBuilder};
+use isa;
 use isa::constraints::*;
 use isa::enc_tables::*;
 use isa::encoding::RecipeSizing;
-use isa;
 use predicates;
-use super::registers::*;
 
 include!(concat!(env!("OUT_DIR"), "/encoding-intel.rs"));
 include!(concat!(env!("OUT_DIR"), "/legalize-intel.rs"));

lib/cretonne/src/isa/intel/mod.rs

@@ -1,22 +1,22 @@
 //! Intel Instruction Set Architectures.
 
-pub mod settings;
 mod abi;
 mod binemit;
 mod enc_tables;
 mod registers;
+pub mod settings;
 
-use binemit::{emit_function, CodeSink, MemoryCodeSink};
 use super::super::settings as shared_settings;
-use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
+use binemit::{emit_function, CodeSink, MemoryCodeSink};
-use isa::Builder as IsaBuilder;
-use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use ir;
+use isa::Builder as IsaBuilder;
+use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
+use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use regalloc;
 use result;
-use timing;
-use std::fmt;
 use std::boxed::Box;
+use std::fmt;
+use timing;
 
 #[allow(dead_code)]
 struct Isa {

lib/cretonne/src/isa/mod.rs

@@ -47,14 +47,14 @@ pub use isa::stack::{StackBase, StackBaseMask, StackRef};
 
 use binemit;
 use flowgraph;
-use settings;
 use ir;
+use isa::enc_tables::Encodings;
 use regalloc;
 use result;
-use timing;
+use settings;
-use isa::enc_tables::Encodings;
-use std::fmt;
 use std::boxed::Box;
+use std::fmt;
+use timing;
 
 #[cfg(build_riscv)]
 mod riscv;
@@ -68,17 +68,16 @@ mod arm32;
 #[cfg(build_arm64)]
 mod arm64;
 
-pub mod registers;
-mod encoding;
-mod enc_tables;
 mod constraints;
+mod enc_tables;
+mod encoding;
+pub mod registers;
 mod stack;
 
 /// Returns a builder that can create a corresponding `TargetIsa`
 /// or `Err(LookupError::Unsupported)` if not enabled.
 macro_rules! isa_builder {
-    ($module:ident, $name:ident) => {
+    ($module:ident, $name:ident) => {{
-        {
         #[cfg($name)]
         fn $name() -> Result<Builder, LookupError> {
             Ok($module::isa_builder())
@@ -88,8 +87,7 @@ macro_rules! isa_builder {
             Err(LookupError::Unsupported)
         }
         $name()
-        }
+    }};
-    };
 }
 
 /// Look for a supported ISA with the given `name`.
@@ -248,8 +246,8 @@ pub trait TargetIsa: fmt::Display {
     fn prologue_epilogue(&self, func: &mut ir::Function) -> result::CtonResult {
         let _tt = timing::prologue_epilogue();
         // This default implementation is unlikely to be good enough.
-        use stack_layout::layout_stack;
         use ir::stackslot::{StackOffset, StackSize};
+        use stack_layout::layout_stack;
 
         let word_size = if self.flags().is_64bit() { 8 } else { 4 };
 

lib/cretonne/src/isa/riscv/abi.rs

@@ -5,13 +5,13 @@
 //!
 //! This doesn't support the soft-float ABI at the moment.
 
+use super::registers::{FPR, GPR};
+use super::settings;
 use abi::{legalize_args, ArgAction, ArgAssigner, ValueConversion};
 use ir::{self, AbiParam, ArgumentExtension, ArgumentLoc, ArgumentPurpose, Type};
 use isa::RegClass;
 use regalloc::AllocatableSet;
 use settings as shared_settings;
-use super::registers::{FPR, GPR};
-use super::settings;
 use std::i32;
 
 struct Args {

lib/cretonne/src/isa/riscv/enc_tables.rs

@@ -1,12 +1,12 @@
 //! Encoding tables for RISC-V.
 
+use super::registers::*;
 use ir;
 use isa;
 use isa::constraints::*;
 use isa::enc_tables::*;
 use isa::encoding::RecipeSizing;
 use predicates;
-use super::registers::*;
 
 // Include the generated encoding tables:
 // - `LEVEL1_RV32`

lib/cretonne/src/isa/riscv/mod.rs

@@ -1,20 +1,20 @@
 //! RISC-V Instruction Set Architecture.
 
-pub mod settings;
 mod abi;
 mod binemit;
 mod enc_tables;
 mod registers;
+pub mod settings;
 
 use super::super::settings as shared_settings;
 use binemit::{emit_function, CodeSink, MemoryCodeSink};
-use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
-use isa::Builder as IsaBuilder;
-use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use ir;
+use isa::Builder as IsaBuilder;
+use isa::enc_tables::{self as shared_enc_tables, lookup_enclist, Encodings};
+use isa::{EncInfo, RegClass, RegInfo, TargetIsa};
 use regalloc;
-use std::fmt;
 use std::boxed::Box;
+use std::fmt;
 
 #[allow(dead_code)]
 struct Isa {
@@ -113,10 +113,10 @@ impl TargetIsa for Isa {
 
 #[cfg(test)]
 mod tests {
-    use settings::{self, Configurable};
-    use isa;
     use ir::{DataFlowGraph, InstructionData, Opcode};
     use ir::{immediates, types};
+    use isa;
+    use settings::{self, Configurable};
     use std::string::{String, ToString};
 
     fn encstr(isa: &isa::TargetIsa, enc: Result<isa::Encoding, isa::Legalize>) -> String {

lib/cretonne/src/isa/stack.rs

@@ -4,8 +4,8 @@
 //! defined in this module expresses the low-level details of accessing a stack slot from an
 //! encoded instruction.
 
-use ir::stackslot::{StackOffset, StackSlotKind, StackSlots};
 use ir::StackSlot;
+use ir::stackslot::{StackOffset, StackSlotKind, StackSlots};
 
 /// A method for referencing a stack slot in the current stack frame.
 ///

lib/cretonne/src/legalizer/boundary.rs

@@ -20,9 +20,9 @@
 use abi::{legalize_abi_value, ValueConversion};
 use cursor::{Cursor, FuncCursor};
 use flowgraph::ControlFlowGraph;
+use ir::instructions::CallInfo;
 use ir::{AbiParam, ArgumentLoc, ArgumentPurpose, DataFlowGraph, Ebb, Function, Inst, InstBuilder,
          SigRef, Signature, Type, Value, ValueLoc};
-use ir::instructions::CallInfo;
 use isa::TargetIsa;
 use legalizer::split::{isplit, vsplit};
 use std::vec::Vec;

lib/cretonne/src/legalizer/heap.rs

@@ -5,8 +5,8 @@
 
 use cursor::{Cursor, FuncCursor};
 use flowgraph::ControlFlowGraph;
-use ir::{self, InstBuilder, MemFlags};
 use ir::condcodes::IntCC;
+use ir::{self, InstBuilder, MemFlags};
 use isa::TargetIsa;
 
 /// Expand a `heap_addr` instruction according to the definition of the heap.

lib/cretonne/src/legalizer/mod.rs

@@ -13,11 +13,11 @@
 //! The legalizer does not deal with register allocation constraints. These constraints are derived
 //! from the encoding recipes, and solved later by the register allocator.
 
+use bitset::BitSet;
 use cursor::{Cursor, FuncCursor};
 use flowgraph::ControlFlowGraph;
 use ir::{self, InstBuilder};
 use isa::TargetIsa;
-use bitset::BitSet;
 use timing;
 
 mod boundary;

lib/cretonne/src/licm.rs

@@ -1,14 +1,14 @@
 //! A Loop Invariant Code Motion optimization pass
 
 use cursor::{Cursor, FuncCursor};
-use ir::{DataFlowGraph, Ebb, Function, Inst, InstBuilder, Layout, Opcode, Type, Value};
-use flowgraph::ControlFlowGraph;
-use std::collections::HashSet;
 use dominator_tree::DominatorTree;
 use entity::{EntityList, ListPool};
+use flowgraph::ControlFlowGraph;
+use ir::{DataFlowGraph, Ebb, Function, Inst, InstBuilder, Layout, Opcode, Type, Value};
 use loop_analysis::{Loop, LoopAnalysis};
-use timing;
+use std::collections::HashSet;
 use std::vec::Vec;
+use timing;
 
 /// Performs the LICM pass by detecting loops within the CFG and moving
 /// loop-invariant instructions out of them.

lib/cretonne/src/loop_analysis.rs

@@ -2,13 +2,13 @@
 //! and parent in the loop tree.
 
 use dominator_tree::DominatorTree;
-use entity::{Keys, PrimaryMap};
 use entity::EntityMap;
+use entity::{Keys, PrimaryMap};
 use flowgraph::ControlFlowGraph;
 use ir::{Ebb, Function, Layout};
 use packed_option::PackedOption;
-use timing;
 use std::vec::Vec;
+use timing;
 
 /// A opaque reference to a code loop.
 #[derive(Copy, Clone, PartialEq, Eq, Hash)]
@@ -226,10 +226,10 @@ impl LoopAnalysis {
 mod test {
 
     use cursor::{Cursor, FuncCursor};
+    use dominator_tree::DominatorTree;
+    use flowgraph::ControlFlowGraph;
     use ir::{types, Function, InstBuilder};
     use loop_analysis::{Loop, LoopAnalysis};
-    use flowgraph::ControlFlowGraph;
-    use dominator_tree::DominatorTree;
     use std::vec::Vec;
 
     #[test]

lib/cretonne/src/postopt.rs

@@ -3,11 +3,11 @@
 #![allow(non_snake_case)]
 
 use cursor::{Cursor, EncCursor};
-use ir::dfg::ValueDef;
-use ir::{Ebb, Function, Inst, InstBuilder, InstructionData, Value};
 use ir::condcodes::{CondCode, FloatCC, IntCC};
-use ir::instructions::{Opcode, ValueList};
+use ir::dfg::ValueDef;
 use ir::immediates::Imm64;
+use ir::instructions::{Opcode, ValueList};
+use ir::{Ebb, Function, Inst, InstBuilder, InstructionData, Value};
 use isa::TargetIsa;
 use timing;
 

lib/cretonne/src/preopt.rs

@@ -3,13 +3,13 @@
 #![allow(non_snake_case)]
 
 use cursor::{Cursor, FuncCursor};
-use ir::dfg::ValueDef;
-use ir::{DataFlowGraph, Function, InstBuilder, InstructionData, Type, Value};
-use ir::Inst;
-use ir::types::{I32, I64};
-use ir::instructions::Opcode;
 use divconst_magic_numbers::{MS32, MS64, MU32, MU64};
 use divconst_magic_numbers::{magicS32, magicS64, magicU32, magicU64};
+use ir::Inst;
+use ir::dfg::ValueDef;
+use ir::instructions::Opcode;
+use ir::types::{I32, I64};
+use ir::{DataFlowGraph, Function, InstBuilder, InstructionData, Type, Value};
 use timing;
 
 //----------------------------------------------------------------------

lib/cretonne/src/print_errors.rs

@@ -1,10 +1,10 @@
 //! Utility routines for pretty-printing error messages.
 
 use ir;
-use verifier;
-use result::CtonError;
 use isa::TargetIsa;
+use result::CtonError;
 use std::fmt::Write;
+use verifier;
 
 /// Pretty-print a verifier error.
 pub fn pretty_verifier_error(

lib/cretonne/src/regalloc/affinity.rs

@@ -8,9 +8,9 @@
 //! subclass. This is just a hint, and the register allocator is allowed to pick a register from a
 //! larger register class instead.
 
-use std::fmt;
 use ir::{AbiParam, ArgumentLoc};
 use isa::{ConstraintKind, OperandConstraint, RegClassIndex, RegInfo, TargetIsa};
+use std::fmt;
 
 /// Preferred register allocation for an SSA value.
 #[derive(Clone, Copy, Debug)]

lib/cretonne/src/regalloc/coalescing.rs

@@ -11,15 +11,15 @@ use dominator_tree::{DominatorTree, DominatorTreePreorder};
 use flowgraph::ControlFlowGraph;
 use ir::{self, InstBuilder, ProgramOrder};
 use ir::{Ebb, ExpandedProgramPoint, Function, Inst, Value};
+use isa::{EncInfo, TargetIsa};
 use regalloc::affinity::Affinity;
 use regalloc::liveness::Liveness;
 use regalloc::virtregs::{VirtReg, VirtRegs};
 use std::cmp;
-use std::iter;
 use std::fmt;
+use std::iter;
 use std::slice;
 use std::vec::Vec;
-use isa::{EncInfo, TargetIsa};
 use timing;
 
 // # Implementation

lib/cretonne/src/regalloc/coloring.rs

@@ -44,10 +44,10 @@
 
 use cursor::{Cursor, EncCursor};
 use dominator_tree::DominatorTree;
-use ir::{Ebb, Function, Inst, Layout, SigRef, Value, ValueLoc};
 use ir::{AbiParam, ArgumentLoc, InstBuilder, ValueDef};
-use isa::{regs_overlap, RegClass, RegInfo, RegUnit};
+use ir::{Ebb, Function, Inst, Layout, SigRef, Value, ValueLoc};
 use isa::{ConstraintKind, EncInfo, OperandConstraint, RecipeConstraints, TargetIsa};
+use isa::{regs_overlap, RegClass, RegInfo, RegUnit};
 use packed_option::PackedOption;
 use regalloc::RegDiversions;
 use regalloc::affinity::Affinity;

lib/cretonne/src/regalloc/diversion.rs

@@ -7,8 +7,8 @@
 //! These register diversions are local to an EBB. No values can be diverted when entering a new
 //! EBB.
 
-use ir::{StackSlot, Value, ValueLoc, ValueLocations};
 use ir::{InstructionData, Opcode};
+use ir::{StackSlot, Value, ValueLoc, ValueLocations};
 use isa::{RegInfo, RegUnit};
 use std::fmt;
 use std::vec::Vec;
@@ -187,8 +187,8 @@ impl<'a> fmt::Display for DisplayDiversions<'a> {
 #[cfg(test)]
 mod tests {
     use super::*;
-    use ir::Value;
     use entity::EntityRef;
+    use ir::Value;
 
     #[test]
     fn inserts() {

lib/cretonne/src/regalloc/liverange.rs

@@ -457,8 +457,8 @@ impl<PO: ProgramOrder> SparseMapValue<Value> for GenLiveRange<PO> {
 mod tests {
     use super::{GenLiveRange, LiveRangeContext};
     use bforest;
-    use ir::{Ebb, Inst, Value};
     use entity::EntityRef;
+    use ir::{Ebb, Inst, Value};
     use ir::{ExpandedProgramPoint, ProgramOrder};
     use std::cmp::Ordering;
     use std::vec::Vec;

lib/cretonne/src/regalloc/mod.rs

@@ -2,11 +2,11 @@
 //!
 //! This module contains data structures and algorithms used for register allocation.
 
-pub mod liverange;
-pub mod liveness;
 pub mod allocatable_set;
-pub mod live_value_tracker;
 pub mod coloring;
+pub mod live_value_tracker;
+pub mod liveness;
+pub mod liverange;
 pub mod virtregs;
 
 mod affinity;

lib/cretonne/src/regalloc/pressure.rs

@@ -269,16 +269,16 @@ impl fmt::Display for Pressure {
 #[cfg(test)]
 #[cfg(build_arm32)]
 mod tests {
+    use super::Pressure;
     use isa::{RegClass, TargetIsa};
     use regalloc::AllocatableSet;
     use std::borrow::Borrow;
-    use super::Pressure;
     use std::boxed::Box;
 
     // Make an arm32 `TargetIsa`, if possible.
     fn arm32() -> Option<Box<TargetIsa>> {
-        use settings;
         use isa;
+        use settings;
 
         let shared_builder = settings::builder();
         let shared_flags = settings::Flags::new(&shared_builder);

lib/cretonne/src/regalloc/reload.rs

@@ -12,16 +12,16 @@
 use cursor::{Cursor, EncCursor};
 use dominator_tree::DominatorTree;
 use entity::{SparseMap, SparseMapValue};
-use ir::{Ebb, Function, Inst, Value};
 use ir::{AbiParam, ArgumentLoc, InstBuilder};
+use ir::{Ebb, Function, Inst, Value};
 use isa::RegClass;
 use isa::{ConstraintKind, EncInfo, Encoding, RecipeConstraints, TargetIsa};
 use regalloc::affinity::Affinity;
 use regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
 use regalloc::liveness::Liveness;
+use std::vec::Vec;
 use timing;
 use topo_order::TopoOrder;
-use std::vec::Vec;
 
 /// Reusable data structures for the reload pass.
 pub struct Reload {

lib/cretonne/src/regalloc/solver.rs

@@ -98,6 +98,7 @@
 //! appropriate candidate among the set of live register values, add it as a variable and start
 //! over.
 
+use super::AllocatableSet;
 use dbg::DisplayList;
 use entity::{SparseMap, SparseMapValue};
 use ir::Value;
@@ -106,7 +107,6 @@ use regalloc::allocatable_set::RegSetIter;
 use std::cmp;
 use std::fmt;
 use std::mem;
-use super::AllocatableSet;
 use std::u16;
 use std::vec::Vec;
 
@@ -1158,17 +1158,17 @@ impl fmt::Display for Solver {
 #[cfg(test)]
 #[cfg(build_arm32)]
 mod tests {
+    use super::{Move, Solver};
     use entity::EntityRef;
     use ir::Value;
     use isa::{RegClass, RegInfo, RegUnit, TargetIsa};
     use regalloc::AllocatableSet;
-    use super::{Move, Solver};
     use std::boxed::Box;
 
     // Make an arm32 `TargetIsa`, if possible.
     fn arm32() -> Option<Box<TargetIsa>> {
-        use settings;
         use isa;
+        use settings;
 
         let shared_builder = settings::builder();
         let shared_flags = settings::Flags::new(&shared_builder);

lib/cretonne/src/regalloc/virtregs.rs

@@ -13,9 +13,9 @@
 
 use dbg::DisplayList;
 use dominator_tree::DominatorTreePreorder;
+use entity::EntityRef;
 use entity::{EntityList, ListPool};
 use entity::{EntityMap, Keys, PrimaryMap};
-use entity::EntityRef;
 use ir::{Function, Value};
 use packed_option::PackedOption;
 use ref_slice::ref_slice;

lib/cretonne/src/result.rs

@@ -1,8 +1,8 @@
 //! Result and error types representing the outcome of compiling a function.
 
-use verifier;
 use std::error::Error as StdError;
 use std::fmt;
+use verifier;
 
 /// A compilation error.
 ///

lib/cretonne/src/settings.rs

@@ -190,8 +190,8 @@ impl<'a> PredicateView<'a> {
 /// This module holds definitions that need to be public so the can be instantiated by generated
 /// code in other modules.
 pub mod detail {
-    use std::fmt;
     use constant_hash;
+    use std::fmt;
 
     /// An instruction group template.
     pub struct Template {
@@ -345,9 +345,9 @@ impl<'a> From<&'a TargetIsa> for FlagsOrIsa<'a> {
 
 #[cfg(test)]
 mod tests {
-    use super::{builder, Flags};
-    use super::Error::*;
     use super::Configurable;
+    use super::Error::*;
+    use super::{builder, Flags};
     use std::string::ToString;
 
     #[test]

lib/cretonne/src/simple_gvn.rs

@@ -4,8 +4,8 @@ use cursor::{Cursor, FuncCursor};
 use dominator_tree::DominatorTree;
 use ir::{Function, Inst, InstructionData, Opcode, Type};
 use scoped_hash_map::ScopedHashMap;
-use timing;
 use std::vec::Vec;
+use timing;
 
 /// Test whether the given opcode is unsafe to even consider for GVN.
 fn trivially_unsafe_for_gvn(opcode: Opcode) -> bool {

lib/cretonne/src/stack_layout.rs

@@ -110,10 +110,10 @@ pub fn layout_stack(frame: &mut StackSlots, alignment: StackSize) -> Result<Stac
 
 #[cfg(test)]
 mod tests {
-    use ir::{StackSlotData, StackSlotKind, StackSlots};
-    use ir::types;
     use super::layout_stack;
     use ir::stackslot::StackOffset;
+    use ir::types;
+    use ir::{StackSlotData, StackSlotKind, StackSlots};
     use result::CtonError;
 
     #[test]

lib/cretonne/src/topo_order.rs

@@ -1,7 +1,7 @@
 //! Topological order of EBBs, according to the dominator tree.
 
-use entity::SparseSet;
 use dominator_tree::DominatorTree;
+use entity::SparseSet;
 use ir::{Ebb, Layout};
 use std::vec::Vec;
 
@@ -89,12 +89,12 @@ impl TopoOrder {
 
 #[cfg(test)]
 mod test {
+    use super::*;
     use cursor::{Cursor, FuncCursor};
-    use flowgraph::ControlFlowGraph;
     use dominator_tree::DominatorTree;
+    use flowgraph::ControlFlowGraph;
     use ir::{Function, InstBuilder};
     use std::iter;
-    use super::*;
 
     #[test]
     fn empty() {

lib/cretonne/src/verifier/flags.rs

@@ -2,13 +2,13 @@
 
 use entity::{EntityMap, SparseSet};
 use flowgraph::ControlFlowGraph;
-use ir::instructions::BranchInfo;
 use ir;
+use ir::instructions::BranchInfo;
 use isa;
 use packed_option::PackedOption;
 use std::result;
-use verifier::{Error, Result};
 use timing;
+use verifier::{Error, Result};
 
 /// Verify that CPU flags are used correctly.
 ///

lib/cretonne/src/verifier/liveness.rs

@@ -1,14 +1,14 @@
 //! Liveness verifier.
 
 use flowgraph::ControlFlowGraph;
-use ir::{ExpandedProgramPoint, Function, Inst, ProgramOrder, ProgramPoint, Value};
 use ir::entities::AnyEntity;
+use ir::{ExpandedProgramPoint, Function, Inst, ProgramOrder, ProgramPoint, Value};
 use isa::TargetIsa;
 use regalloc::liveness::Liveness;
 use regalloc::liverange::LiveRange;
 use std::cmp::Ordering;
-use verifier::Result;
 use timing;
+use verifier::Result;
 
 /// Verify liveness information for `func`.
 ///

lib/cretonne/src/verifier/locations.rs

@@ -4,8 +4,8 @@ use ir;
 use isa;
 use regalloc::RegDiversions;
 use regalloc::liveness::Liveness;
-use verifier::Result;
 use timing;
+use verifier::Result;
 
 /// Verify value locations for `func`.
 ///

lib/cretonne/src/verifier/mod.rs

@@ -55,26 +55,26 @@
 //! - Swizzle and shuffle instructions take a variable number of lane arguments. The number
 //!   of arguments must match the destination type, and the lane indexes must be in range.
 
+use self::flags::verify_flags;
 use dbg::DisplayList;
 use dominator_tree::DominatorTree;
 use entity::SparseSet;
 use flowgraph::ControlFlowGraph;
+use ir;
 use ir::entities::AnyEntity;
 use ir::instructions::{BranchInfo, CallInfo, InstructionFormat, ResolvedConstraint};
 use ir::{types, ArgumentLoc, Ebb, FuncRef, Function, GlobalVar, Inst, JumpTable, Opcode, SigRef,
          StackSlot, StackSlotKind, Type, Value, ValueDef, ValueList, ValueLoc};
-use ir;
 use isa::TargetIsa;
 use iterators::IteratorExtras;
-use self::flags::verify_flags;
 use settings::{Flags, FlagsOrIsa};
 use std::cmp::Ordering;
 use std::collections::BTreeSet;
 use std::error as std_error;
 use std::fmt::{self, Display, Formatter, Write};
 use std::result;
-use std::vec::Vec;
 use std::string::String;
+use std::vec::Vec;
 use timing;
 
 pub use self::cssa::verify_cssa;
@@ -1155,22 +1155,25 @@ impl<'a> Verifier<'a> {
 #[cfg(test)]
 mod tests {
     use super::{Error, Verifier};
+    use entity::EntityList;
     use ir::Function;
     use ir::instructions::{InstructionData, Opcode};
-    use entity::EntityList;
     use settings;
 
     macro_rules! assert_err_with_msg {
-        ($e:expr, $msg:expr) => (
+        ($e:expr, $msg:expr) => {
             match $e {
-                Ok(_) => { panic!("Expected an error!") },
+                Ok(_) => panic!("Expected an error!"),
                 Err(Error { message, .. }) => {
                     if !message.contains($msg) {
-                       panic!(format!("'{}' did not contain the substring '{}'", message, $msg));
+                        panic!(format!(
+                            "'{}' did not contain the substring '{}'",
+                            message, $msg
+                        ));
                     }
                 }
             }
-        )
+        };
     }
 
     #[test]

lib/cretonne/src/write.rs

@@ -5,9 +5,9 @@
 
 use ir::{DataFlowGraph, Ebb, Function, Inst, SigRef, Type, Value, ValueDef};
 use isa::{RegInfo, TargetIsa};
+use packed_option::ReservedValue;
 use std::fmt::{self, Error, Result, Write};
 use std::result;
-use packed_option::ReservedValue;
 use std::string::String;
 
 /// Write `func` to `w` as equivalent text.
@@ -451,8 +451,8 @@ impl<'a> fmt::Display for DisplayValues<'a> {
 
 #[cfg(test)]
 mod tests {
-    use ir::{ExternalName, Function, StackSlotData, StackSlotKind};
     use ir::types;
+    use ir::{ExternalName, Function, StackSlotData, StackSlotKind};
     use std::string::ToString;
 
     #[test]

lib/filetests/src/concurrent.rs

@@ -4,13 +4,13 @@
 //! concurrently.
 
 use cretonne::timing;
+use num_cpus;
 use std::panic::catch_unwind;
 use std::path::{Path, PathBuf};
 use std::sync::mpsc::{channel, Receiver, Sender};
 use std::sync::{Arc, Mutex};
 use std::thread;
 use std::time::Duration;
-use num_cpus;
 use {runone, TestResult};
 
 /// Request sent to worker threads contains jobid and path.

lib/filetests/src/lib.rs

@@ -14,16 +14,16 @@ extern crate cton_reader;
 extern crate filecheck;
 extern crate num_cpus;
 
-use std::path::Path;
-use std::time;
 use cton_reader::TestCommand;
 use runner::TestRunner;
+use std::path::Path;
+use std::time;
 
 mod concurrent;
+mod match_directive;
 mod runner;
 mod runone;
 mod subtest;
-mod match_directive;
 
 mod test_binemit;
 mod test_cat;

lib/filetests/src/runner.rs

@@ -3,13 +3,13 @@
 //! This module implements the `TestRunner` struct which manages executing tests as well as
 //! scanning directories for tests.
 
+use concurrent::{ConcurrentRunner, Reply};
 use std::error::Error;
-use std::fmt::{self, Display};
 use std::ffi::OsStr;
+use std::fmt::{self, Display};
 use std::path::{Path, PathBuf};
 use std::time;
 use {runone, TestResult};
-use concurrent::{ConcurrentRunner, Reply};
 
 /// Timeout in seconds when we're not making progress.
 const TIMEOUT_PANIC: usize = 10;

lib/filetests/src/runone.rs

@@ -1,20 +1,20 @@
 //! Run the tests in a single test file.
 
-use std::borrow::Cow;
-use std::path::Path;
-use std::time;
-use std::io::{self, Read};
-use std::fs;
 use cretonne::ir::Function;
 use cretonne::isa::TargetIsa;
+use cretonne::print_errors::pretty_verifier_error;
 use cretonne::settings::Flags;
 use cretonne::timing;
 use cretonne::verify_function;
-use cretonne::print_errors::pretty_verifier_error;
-use cton_reader::parse_test;
 use cton_reader::IsaSpec;
-use {new_subtest, TestResult};
+use cton_reader::parse_test;
+use std::borrow::Cow;
+use std::fs;
+use std::io::{self, Read};
+use std::path::Path;
+use std::time;
 use subtest::{Context, Result, SubTest};
+use {new_subtest, TestResult};
 
 /// Read an entire file into a string.
 fn read_to_string<P: AsRef<Path>>(path: P) -> io::Result<String> {

lib/filetests/src/subtest.rs

@@ -1,12 +1,12 @@
 //! `SubTest` trait.
 
-use std::result;
-use std::borrow::Cow;
 use cretonne::ir::Function;
 use cretonne::isa::TargetIsa;
 use cretonne::settings::{Flags, FlagsOrIsa};
 use cton_reader::{Comment, Details};
 use filecheck::{Checker, CheckerBuilder, NO_VARIABLES};
+use std::borrow::Cow;
+use std::result;
 
 pub type Result<T> = result::Result<T, String>;
 

lib/filetests/src/test_binemit.rs

@@ -3,18 +3,18 @@
 //! The `binemit` test command generates binary machine code for every instruction in the input
 //! functions and compares the results to the expected output.
 
-use std::borrow::Cow;
-use std::collections::HashMap;
-use std::fmt::Write;
 use cretonne::binemit;
+use cretonne::binemit::RegDiversions;
 use cretonne::dbg::DisplayList;
 use cretonne::ir;
 use cretonne::ir::entities::AnyEntity;
-use cretonne::binemit::RegDiversions;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{Context, Result, SubTest};
 use match_directive::match_directive;
+use std::borrow::Cow;
+use std::collections::HashMap;
+use std::fmt::Write;
+use subtest::{Context, Result, SubTest};
 
 struct TestBinEmit;
 

lib/filetests/src/test_cat.rs

@@ -1,8 +1,8 @@
 //! The `cat` subtest.
 
-use std::borrow::Cow;
 use cretonne::ir::Function;
 use cton_reader::TestCommand;
+use std::borrow::Cow;
 use subtest::{self, Context, Result as STResult, SubTest};
 
 /// Object implementing the `test cat` sub-test.

lib/filetests/src/test_compile.rs

@@ -2,14 +2,14 @@
 //!
 //! The `compile` test command runs each function through the full code generator pipeline
 
+use cretonne;
 use cretonne::binemit;
 use cretonne::ir;
-use cretonne;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestCompile;
 

lib/filetests/src/test_dce.rs

@@ -5,13 +5,13 @@
 //!
 //! The resulting function is sent to `filecheck`.
 
-use cretonne::ir::Function;
 use cretonne;
+use cretonne::ir::Function;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestDCE;
 

lib/filetests/src/test_domtree.rs

@@ -17,12 +17,12 @@ use cretonne::flowgraph::ControlFlowGraph;
 use cretonne::ir::Function;
 use cretonne::ir::entities::AnyEntity;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
+use match_directive::match_directive;
 use std::borrow::{Borrow, Cow};
 use std::collections::HashMap;
 use std::fmt::{self, Write};
 use std::result;
-use match_directive::match_directive;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestDomtree;
 

lib/filetests/src/test_legalizer.rs

@@ -3,13 +3,13 @@
 //! The `test legalizer` test command runs each function through `legalize_function()` and sends
 //! the result to filecheck.
 
-use std::borrow::Cow;
 use cretonne;
 use cretonne::ir::Function;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
+use std::borrow::Cow;
 use std::fmt::Write;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestLegalizer;
 

lib/filetests/src/test_licm.rs

@@ -5,13 +5,13 @@
 //!
 //! The resulting function is sent to `filecheck`.
 
-use cretonne::ir::Function;
 use cretonne;
+use cretonne::ir::Function;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestLICM;
 

lib/filetests/src/test_postopt.rs

@@ -2,13 +2,13 @@
 //!
 //! The resulting function is sent to `filecheck`.
 
-use cretonne::ir::Function;
 use cretonne;
+use cretonne::ir::Function;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestPostopt;
 

lib/filetests/src/test_preopt.rs

@@ -2,13 +2,13 @@
 //!
 //! The resulting function is sent to `filecheck`.
 
-use cretonne::ir::Function;
 use cretonne;
+use cretonne::ir::Function;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestPreopt;
 

lib/filetests/src/test_print_cfg.rs

@@ -5,8 +5,8 @@
 
 use std::borrow::Cow;
 
-use cretonne::ir::Function;
 use cretonne::cfg_printer::CFGPrinter;
+use cretonne::ir::Function;
 use cton_reader::TestCommand;
 use subtest::{self, Context, Result as STResult, SubTest};
 

lib/filetests/src/test_regalloc.rs

@@ -5,13 +5,13 @@
 //!
 //! The resulting function is sent to `filecheck`.
 
-use cretonne::ir::Function;
 use cretonne;
+use cretonne::ir::Function;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestRegalloc;
 

lib/filetests/src/test_simple_gvn.rs

@@ -5,13 +5,13 @@
 //!
 //! The resulting function is sent to `filecheck`.
 
-use cretonne::ir::Function;
 use cretonne;
+use cretonne::ir::Function;
 use cretonne::print_errors::pretty_error;
 use cton_reader::TestCommand;
-use subtest::{run_filecheck, Context, Result, SubTest};
 use std::borrow::Cow;
 use std::fmt::Write;
+use subtest::{run_filecheck, Context, Result, SubTest};
 
 struct TestSimpleGVN;
 

lib/filetests/src/test_verifier.rs

@@ -9,12 +9,12 @@
 //! This annotation means that the verifier is expected to given an error for the jump instruction
 //! containing the substring "jump to non-existent EBB".
 
-use std::borrow::{Borrow, Cow};
-use cretonne::verify_function;
 use cretonne::ir::Function;
+use cretonne::verify_function;
 use cton_reader::TestCommand;
-use subtest::{Context, Result, SubTest};
 use match_directive::match_directive;
+use std::borrow::{Borrow, Cow};
+use subtest::{Context, Result, SubTest};
 
 struct TestVerifier;
 

lib/frontend/src/frontend.rs

@@ -1,14 +1,14 @@
 //! A frontend for building Cretonne IR from other languages.
 use cretonne::cursor::{Cursor, FuncCursor};
+use cretonne::entity::{EntityMap, EntityRef, EntitySet};
 use cretonne::ir;
+use cretonne::ir::function::DisplayFunction;
 use cretonne::ir::{DataFlowGraph, Ebb, ExtFuncData, FuncRef, Function, GlobalVar, GlobalVarData,
                    Heap, HeapData, Inst, InstBuilderBase, InstructionData, JumpTable,
                    JumpTableData, SigRef, Signature, StackSlot, StackSlotData, Type, Value};
-use cretonne::ir::function::DisplayFunction;
 use cretonne::isa::TargetIsa;
-use ssa::{Block, SSABuilder, SideEffects};
-use cretonne::entity::{EntityMap, EntityRef, EntitySet};
 use cretonne::packed_option::PackedOption;
+use ssa::{Block, SSABuilder, SideEffects};
 
 /// Structure used for translating a series of functions into Cretonne IR.
 ///
@@ -592,13 +592,13 @@ where
 #[cfg(test)]
 mod tests {
 
-    use cretonne::entity::EntityRef;
-    use cretonne::ir::{AbiParam, CallConv, ExternalName, Function, InstBuilder, Signature};
-    use cretonne::ir::types::*;
-    use frontend::{FunctionBuilder, FunctionBuilderContext};
-    use cretonne::verifier::verify_function;
-    use cretonne::settings;
     use Variable;
+    use cretonne::entity::EntityRef;
+    use cretonne::ir::types::*;
+    use cretonne::ir::{AbiParam, CallConv, ExternalName, Function, InstBuilder, Signature};
+    use cretonne::settings;
+    use cretonne::verifier::verify_function;
+    use frontend::{FunctionBuilder, FunctionBuilderContext};
 
     fn sample_function(lazy_seal: bool) {
         let mut sig = Signature::new(CallConv::SystemV);