Begin an Intel-specific instruction group.

Add instructions representing Intel's division instructions which use a
numerator that is twice as wide as the denominator and produce both the
quotient and remainder.

Add encodings for the x86_[su]divmodx instructions.

cranelift/docs/cton_domain.py

@@ -271,7 +271,10 @@ class InstDocumenter(sphinx.ext.autodoc.Documenter):
         return False
 
     def resolve_name(self, modname, parents, path, base):
-        return 'base.instructions', [base]
+        if path:
+            return path.rstrip('.'), [base]
+        else:
+            return 'base.instructions', [base]
 
     def format_signature(self):
         inst = self.object

cranelift/docs/langref.rst

@@ -775,15 +775,31 @@ the target ISA.
 .. autoinst:: isplit
 .. autoinst:: iconcat
 
-Base instruction group
-======================
+ISA-specific instructions
+=========================
+
+Target ISAs can define supplemental instructions that do not make sense to
+support generally.
+
+Intel
+-----
+
+Instructions that can only be used by the Intel target ISA.
+
+.. autoinst:: isa.intel.instructions.sdivmodx
+.. autoinst:: isa.intel.instructions.udivmodx
+
+Instruction groups
+==================
 
 All of the shared instructions are part of the :instgroup:`base` instruction
 group.
 
 .. autoinstgroup:: base.instructions.GROUP
 
-Target ISAs may define further instructions in their own instruction groups.
+Target ISAs may define further instructions in their own instruction groups:
+
+.. autoinstgroup:: isa.intel.instructions.GROUP
 
 Implementation limits
 =====================

cranelift/filetests/isa/intel/binary32.cton

@@ -112,6 +112,19 @@ ebb0:
     ; asm: imull %ecx, %esi
     [-,%rsi]             v51 = imul v2, v1       ; bin: 0f af f1
 
+    ; asm: movl $1, %eax
+    [-,%rax]      v52 = iconst.i32 1                    ; bin: b8 00000001
+    ; asm: movl $2, %edx
+    [-,%rdx]      v53 = iconst.i32 2                    ; bin: ba 00000002
+    ; asm: idivl %ecx
+    [-,%rax,%rdx] v54, v55 = x86_sdivmodx v52, v53, v1  ; bin: f7 f9
+    ; asm: idivl %esi
+    [-,%rax,%rdx] v56, v57 = x86_sdivmodx v52, v53, v2  ; bin: f7 fe
+    ; asm: divl %ecx
+    [-,%rax,%rdx] v58, v59 = x86_udivmodx v52, v53, v1  ; bin: f7 f1
+    ; asm: divl %esi
+    [-,%rax,%rdx] v60, v61 = x86_udivmodx v52, v53, v2  ; bin: f7 f6
+
     ; Register copies.
 
     ; asm: movl %esi, %ecx

cranelift/filetests/isa/intel/binary64.cton

@@ -154,6 +154,21 @@ ebb0:
     ; asm: imulq %rcx, %r10
     [-,%r10]             v122 = imul v3, v1       ; bin: 4c 0f af d1
 
+    [-,%rax]      v130 = iconst.i64 1
+    [-,%rdx]      v131 = iconst.i64 2
+    ; asm: idivq %rcx
+    [-,%rax,%rdx] v132, v133 = x86_sdivmodx v130, v131, v1  ; bin: 48 f7 f9
+    ; asm: idivq %rsi
+    [-,%rax,%rdx] v134, v135 = x86_sdivmodx v130, v131, v2  ; bin: 48 f7 fe
+    ; asm: idivq %r10
+    [-,%rax,%rdx] v136, v137 = x86_sdivmodx v130, v131, v3  ; bin: 49 f7 fa
+    ; asm: divq %rcx
+    [-,%rax,%rdx] v138, v139 = x86_udivmodx v130, v131, v1  ; bin: 48 f7 f1
+    ; asm: divq %rsi
+    [-,%rax,%rdx] v140, v141 = x86_udivmodx v130, v131, v2  ; bin: 48 f7 f6
+    ; asm: divq %r10
+    [-,%rax,%rdx] v142, v143 = x86_udivmodx v130, v131, v3  ; bin: 49 f7 f2
+
     ; Bit-counting instructions.
 
     ; asm: popcntq %rsi, %rcx
@@ -331,6 +346,21 @@ ebb0:
     ; asm: imull %ecx, %r10d
     [-,%r10]             v122 = imul v3, v1       ; bin: 44 0f af d1
 
+    [-,%rax]      v130 = iconst.i32 1
+    [-,%rdx]      v131 = iconst.i32 2
+    ; asm: idivl %rcx
+    [-,%rax,%rdx] v132, v133 = x86_sdivmodx v130, v131, v1  ; bin: 40 f7 f9
+    ; asm: idivl %rsi
+    [-,%rax,%rdx] v134, v135 = x86_sdivmodx v130, v131, v2  ; bin: 40 f7 fe
+    ; asm: idivl %r10d
+    [-,%rax,%rdx] v136, v137 = x86_sdivmodx v130, v131, v3  ; bin: 41 f7 fa
+    ; asm: divl %rcx
+    [-,%rax,%rdx] v138, v139 = x86_udivmodx v130, v131, v1  ; bin: 40 f7 f1
+    ; asm: divl %rsi
+    [-,%rax,%rdx] v140, v141 = x86_udivmodx v130, v131, v2  ; bin: 40 f7 f6
+    ; asm: divl %r10d
+    [-,%rax,%rdx] v142, v143 = x86_udivmodx v130, v131, v3  ; bin: 41 f7 f2
+
     ; Bit-counting instructions.
 
     ; asm: popcntl %esi, %ecx