Update paths for the meta => meta-python rename.

This commit is contained in:
Dan Gohman
2018-08-01 05:05:33 -07:00
parent 3a550d185f
commit c42bed7452
18 changed files with 40 additions and 39 deletions

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@@ -3,7 +3,7 @@
use settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/codegen/meta/gen_settings.py`. This file contains a public
// Include code generated by `lib/codegen/meta-python/gen_settings.py`. This file contains a public
// `Flags` struct with an impl for all of the settings defined in
// `lib/codegen/meta/isa/arm32/settings.py`.
// `lib/codegen/meta-python/isa/arm32/settings.py`.
include!(concat!(env!("OUT_DIR"), "/settings-arm32.rs"));

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@@ -3,7 +3,7 @@
use settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/codegen/meta/gen_settings.py`. This file contains a public
// Include code generated by `lib/codegen/meta-python/gen_settings.py`. This file contains a public
// `Flags` struct with an impl for all of the settings defined in
// `lib/codegen/meta/isa/arm64/settings.py`.
// `lib/codegen/meta-python/isa/arm64/settings.py`.
include!(concat!(env!("OUT_DIR"), "/settings-arm64.rs"));

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@@ -1,7 +1,7 @@
//! Support types for generated encoding tables.
//!
//! This module contains types and functions for working with the encoding tables generated by
//! `lib/codegen/meta/gen_encoding.py`.
//! `lib/codegen/meta-python/gen_encoding.py`.
use constant_hash::{probe, Table};
use ir::{Function, InstructionData, Opcode, Type};
@@ -164,10 +164,10 @@ where
/// Encoding lists are represented as sequences of u16 words.
pub type EncListEntry = u16;
/// Number of bits used to represent a predicate. c.f. `meta/gen_encoding.py`.
/// Number of bits used to represent a predicate. c.f. `meta-python/gen_encoding.py`.
const PRED_BITS: u8 = 12;
const PRED_MASK: usize = (1 << PRED_BITS) - 1;
/// First code word representing a predicate check. c.f. `meta/gen_encoding.py`.
/// First code word representing a predicate check. c.f. `meta-python/gen_encoding.py`.
const PRED_START: usize = 0x1000;
/// An iterator over legal encodings for the instruction.

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@@ -17,19 +17,19 @@ pub type RegUnit = u16;
/// The size of this type is determined by the target ISA that has the most register units defined.
/// Currently that is arm32 which has 64+16 units.
///
/// This type should be coordinated with meta/cdsl/registers.py.
/// This type should be coordinated with meta-python/cdsl/registers.py.
pub type RegUnitMask = [u32; 3];
/// A bit mask indexed by register classes.
///
/// The size of this type is determined by the ISA with the most register classes.
///
/// This type should be coordinated with meta/cdsl/isa.py.
/// This type should be coordinated with meta-python/cdsl/isa.py.
pub type RegClassMask = u32;
/// Guaranteed maximum number of top-level register classes with pressure tracking in any ISA.
///
/// This can be increased, but should be coordinated with meta/cdsl/isa.py.
/// This can be increased, but should be coordinated with meta-python/cdsl/isa.py.
pub const MAX_TRACKED_TOPRCS: usize = 4;
/// The register units in a target ISA are divided into disjoint register banks. Each bank covers a

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@@ -3,9 +3,9 @@
use settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/codegen/meta/gen_settings.py`. This file contains a public
// Include code generated by `lib/codegen/meta-python/gen_settings.py`. This file contains a public
// `Flags` struct with an impl for all of the settings defined in
// `lib/codegen/meta/isa/riscv/settings.py`.
// `lib/codegen/meta-python/isa/riscv/settings.py`.
include!(concat!(env!("OUT_DIR"), "/settings-riscv.rs"));
#[cfg(test)]

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@@ -3,9 +3,9 @@
use settings::{self, detail, Builder};
use std::fmt;
// Include code generated by `lib/codegen/meta/gen_settings.py`. This file contains a public
// Include code generated by `lib/codegen/meta-python/gen_settings.py`. This file contains a public
// `Flags` struct with an impl for all of the settings defined in
// `lib/codegen/meta/isa/x86/settings.py`.
// `lib/codegen/meta-python/isa/x86/settings.py`.
include!(concat!(env!("OUT_DIR"), "/settings-x86.rs"));
#[cfg(test)]