aarch64: Add basic i128 bit ops to the AArch64 backend

Currently we just basically use a two instruction version of the same i64 ops.
IMMLogic doesn't really support multiple register inputs, so its left as a TODO for future optimizations.

cranelift/filetests/filetests/isa/aarch64/bitops.clif

@@ -293,3 +293,94 @@ block0:
 ; nextln: sbfx w0, w0, #0, #1
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
+
+function %bnot_i128(i128) -> i128 {
+block0(v0: i128):
+    v1 = bnot v0
+    return v1
+}
+
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: orn x0, xzr, x0
+; nextln: orn x1, xzr, x1
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %band_i128(i128, i128) -> i128 {
+block0(v0: i128, v1: i128):
+    v2 = band v0, v1
+    return v2
+}
+
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: and x0, x0, x2
+; nextln: and x1, x1, x3
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %bor_i128(i128, i128) -> i128 {
+block0(v0: i128, v1: i128):
+    v2 = bor v0, v1
+    return v2
+}
+
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: orr x0, x0, x2
+; nextln: orr x1, x1, x3
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %bxor_i128(i128, i128) -> i128 {
+block0(v0: i128, v1: i128):
+    v2 = bxor v0, v1
+    return v2
+}
+
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: eor x0, x0, x2
+; nextln: eor x1, x1, x3
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %band_not_i128(i128, i128) -> i128 {
+block0(v0: i128, v1: i128):
+    v2 = band_not v0, v1
+    return v2
+}
+
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: bic x0, x0, x2
+; nextln: bic x1, x1, x3
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %bor_not_i128(i128, i128) -> i128 {
+block0(v0: i128, v1: i128):
+    v2 = bor_not v0, v1
+    return v2
+}
+
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: orn x0, x0, x2
+; nextln: orn x1, x1, x3
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %bxor_not_i128(i128, i128) -> i128 {
+block0(v0: i128, v1: i128):
+    v2 = bxor_not v0, v1
+    return v2
+}
+
+; check: stp fp, lr, [sp, #-16]!
+; nextln: mov fp, sp
+; nextln: eon x0, x0, x2
+; nextln: eon x1, x1, x3
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret