x64: Add most remaining AVX lowerings (#5819)
* x64: Add most remaining AVX lowerings This commit goes through `inst.isle` and adds a corresponding AVX lowering for most SSE lowerings. I opted to skip instructions where the SSE lowering didn't read/modify a register, such as `roundps`. I think that AVX will benefit these instructions when there's load-merging since AVX doesn't require alignment, but I've deferred that work to a future PR. Otherwise though in this PR I think all (or almost all) of the 3-operand forms of AVX instructions are supported with their SSE counterparts. This should ideally improve codegen slightly by removing register pressure and the need for `movdqa` between registers. I've attempted to ensure that there's at least one codegen test for all the new instructions. As a side note, the recent capstone integration into `precise-output` tests helped me catch a number of encoding bugs much earlier than otherwise, so I've found that incredibly useful in tests! * Move `vpinsr*` instructions to their own variant Use true `XmmMem` and `GprMem` types in the instruction as well to get more type-level safety for what goes where. * Remove `Inst::produces_const` accessor Instead of conditionally defining regalloc and various other operations instead add dedicated `MInst` variants for operations which are intended to produce a constant to have more clear interactions with regalloc and printing and such. * Fix tests * Register traps in `MachBuffer` for load-folding ops This adds a missing `add_trap` to encoding of VEX instructions with memory operands to ensure that if they cause a segfault that there's appropriate metadata for Wasmtime to understand that the instruction could in fact trap. This fixes a fuzz test case found locally where v8 trapped and Wasmtime didn't catch the signal and crashed the fuzzer.
This commit is contained in:
Alex Crichton
@@ -148,16 +148,10 @@ pub(crate) fn emit(
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src2,
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dst: reg_g,
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} => {
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let (reg_g, src2) = if inst.produces_const() {
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let reg_g = allocs.next(reg_g.to_reg().to_reg());
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(reg_g, RegMemImm::reg(reg_g))
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} else {
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let src1 = allocs.next(src1.to_reg());
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let reg_g = allocs.next(reg_g.to_reg().to_reg());
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debug_assert_eq!(src1, reg_g);
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let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
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(reg_g, src2)
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};
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let src1 = allocs.next(src1.to_reg());
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let reg_g = allocs.next(reg_g.to_reg().to_reg());
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debug_assert_eq!(src1, reg_g);
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let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
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let rex = RexFlags::from(*size);
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if *op == AluRmiROpcode::Mul {
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@@ -253,6 +247,23 @@ pub(crate) fn emit(
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}
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}
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Inst::AluConstOp { op, size, dst } => {
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let dst = allocs.next(dst.to_reg().to_reg());
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emit(
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&Inst::AluRmiR {
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size: *size,
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op: *op,
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dst: Writable::from_reg(Gpr::new(dst).unwrap()),
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src1: Gpr::new(dst).unwrap(),
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src2: Gpr::new(dst).unwrap().into(),
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},
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allocs,
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sink,
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info,
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state,
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);
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}
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Inst::AluRM {
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size,
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src1_dst,
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@@ -1837,16 +1848,10 @@ pub(crate) fn emit(
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src2: src_e,
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dst: reg_g,
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} => {
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let (src_e, reg_g) = if inst.produces_const() {
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let reg_g = allocs.next(reg_g.to_reg().to_reg());
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(RegMem::Reg { reg: reg_g }, reg_g)
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} else {
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let src1 = allocs.next(src1.to_reg());
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let reg_g = allocs.next(reg_g.to_reg().to_reg());
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let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
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debug_assert_eq!(src1, reg_g);
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(src_e, reg_g)
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};
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let src1 = allocs.next(src1.to_reg());
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let reg_g = allocs.next(reg_g.to_reg().to_reg());
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let src_e = src_e.clone().to_reg_mem().with_allocs(allocs);
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debug_assert_eq!(src1, reg_g);
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let rex = RexFlags::clear_w();
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let (prefix, opcode, length) = match op {
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@@ -1959,6 +1964,22 @@ pub(crate) fn emit(
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}
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}
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Inst::XmmConstOp { op, dst } => {
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let dst = allocs.next(dst.to_reg().to_reg());
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emit(
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&Inst::XmmRmR {
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op: *op,
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dst: Writable::from_reg(Xmm::new(dst).unwrap()),
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src1: Xmm::new(dst).unwrap(),
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src2: Xmm::new(dst).unwrap().into(),
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},
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allocs,
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sink,
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info,
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state,
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);
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}
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Inst::XmmRmRBlend {
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op,
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src1,
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@@ -1998,6 +2019,9 @@ pub(crate) fn emit(
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src2,
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dst,
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} => {
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use LegacyPrefixes as LP;
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use OpcodeMap as OM;
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let dst = allocs.next(dst.to_reg().to_reg());
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let src1 = allocs.next(src1.to_reg());
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let src2 = src2.clone().to_reg_mem_imm().with_allocs(allocs);
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@@ -2008,8 +2032,15 @@ pub(crate) fn emit(
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// `opcode_ext`, so handle that specially here.
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RegMemImm::Imm { simm32 } => {
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let (opcode, opcode_ext, prefix) = match op {
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AvxOpcode::Vpsrlw => (0x71, 2, LegacyPrefixes::_66),
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AvxOpcode::Vpsrld => (0x72, 2, LegacyPrefixes::_66),
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_ => panic!("unexpected avx opcode with immediate {op:?}"),
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AvxOpcode::Vpsrlq => (0x73, 2, LegacyPrefixes::_66),
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AvxOpcode::Vpsllw => (0x71, 6, LegacyPrefixes::_66),
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AvxOpcode::Vpslld => (0x72, 6, LegacyPrefixes::_66),
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AvxOpcode::Vpsllq => (0x73, 6, LegacyPrefixes::_66),
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AvxOpcode::Vpsraw => (0x71, 4, LegacyPrefixes::_66),
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AvxOpcode::Vpsrad => (0x72, 4, LegacyPrefixes::_66),
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_ => panic!("unexpected rmi_r_vex opcode with immediate {op:?}"),
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};
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VexInstruction::new()
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.length(VexVectorLength::V128)
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@@ -2029,18 +2060,104 @@ pub(crate) fn emit(
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}
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RegMemImm::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
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};
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let (prefix, opcode) = match op {
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AvxOpcode::Vminps => (LegacyPrefixes::None, 0x5D),
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AvxOpcode::Vandnps => (LegacyPrefixes::None, 0x55),
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AvxOpcode::Vorps => (LegacyPrefixes::None, 0x56),
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AvxOpcode::Vpsrld => (LegacyPrefixes::_66, 0xD2),
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let (prefix, map, opcode) = match op {
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AvxOpcode::Vminps => (LP::None, OM::_0F, 0x5D),
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AvxOpcode::Vminpd => (LP::_66, OM::_0F, 0x5D),
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AvxOpcode::Vmaxps => (LP::None, OM::_0F, 0x5F),
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AvxOpcode::Vmaxpd => (LP::_66, OM::_0F, 0x5F),
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AvxOpcode::Vandnps => (LP::None, OM::_0F, 0x55),
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AvxOpcode::Vandnpd => (LP::_66, OM::_0F, 0x55),
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AvxOpcode::Vpandn => (LP::_66, OM::_0F, 0xDF),
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AvxOpcode::Vpsrlw => (LP::_66, OM::_0F, 0xD1),
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AvxOpcode::Vpsrld => (LP::_66, OM::_0F, 0xD2),
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AvxOpcode::Vpsrlq => (LP::_66, OM::_0F, 0xD3),
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AvxOpcode::Vpaddb => (LP::_66, OM::_0F, 0xFC),
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AvxOpcode::Vpaddw => (LP::_66, OM::_0F, 0xFD),
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AvxOpcode::Vpaddd => (LP::_66, OM::_0F, 0xFE),
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AvxOpcode::Vpaddq => (LP::_66, OM::_0F, 0xD4),
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AvxOpcode::Vpaddsb => (LP::_66, OM::_0F, 0xEC),
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AvxOpcode::Vpaddsw => (LP::_66, OM::_0F, 0xED),
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AvxOpcode::Vpaddusb => (LP::_66, OM::_0F, 0xDC),
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AvxOpcode::Vpaddusw => (LP::_66, OM::_0F, 0xDD),
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AvxOpcode::Vpsubb => (LP::_66, OM::_0F, 0xF8),
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AvxOpcode::Vpsubw => (LP::_66, OM::_0F, 0xF9),
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AvxOpcode::Vpsubd => (LP::_66, OM::_0F, 0xFA),
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AvxOpcode::Vpsubq => (LP::_66, OM::_0F, 0xFB),
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AvxOpcode::Vpsubsb => (LP::_66, OM::_0F, 0xE8),
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AvxOpcode::Vpsubsw => (LP::_66, OM::_0F, 0xE9),
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AvxOpcode::Vpsubusb => (LP::_66, OM::_0F, 0xD8),
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AvxOpcode::Vpsubusw => (LP::_66, OM::_0F, 0xD9),
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AvxOpcode::Vpavgb => (LP::_66, OM::_0F, 0xE0),
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AvxOpcode::Vpavgw => (LP::_66, OM::_0F, 0xE3),
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AvxOpcode::Vpand => (LP::_66, OM::_0F, 0xDB),
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AvxOpcode::Vandps => (LP::None, OM::_0F, 0x54),
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AvxOpcode::Vandpd => (LP::_66, OM::_0F, 0x54),
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AvxOpcode::Vpor => (LP::_66, OM::_0F, 0xEB),
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AvxOpcode::Vorps => (LP::None, OM::_0F, 0x56),
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AvxOpcode::Vorpd => (LP::_66, OM::_0F, 0x56),
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AvxOpcode::Vpxor => (LP::_66, OM::_0F, 0xEF),
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AvxOpcode::Vxorps => (LP::None, OM::_0F, 0x57),
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AvxOpcode::Vxorpd => (LP::_66, OM::_0F, 0x57),
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AvxOpcode::Vpmullw => (LP::_66, OM::_0F, 0xD5),
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AvxOpcode::Vpmulld => (LP::_66, OM::_0F38, 0x40),
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AvxOpcode::Vpmulhw => (LP::_66, OM::_0F, 0xE5),
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AvxOpcode::Vpmulhrsw => (LP::_66, OM::_0F38, 0x0B),
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AvxOpcode::Vpmulhuw => (LP::_66, OM::_0F, 0xE4),
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AvxOpcode::Vpmuldq => (LP::_66, OM::_0F38, 0x28),
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AvxOpcode::Vpmuludq => (LP::_66, OM::_0F, 0xF4),
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AvxOpcode::Vpunpckhwd => (LP::_66, OM::_0F, 0x69),
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AvxOpcode::Vpunpcklwd => (LP::_66, OM::_0F, 0x61),
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AvxOpcode::Vunpcklps => (LP::None, OM::_0F, 0x14),
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AvxOpcode::Vaddps => (LP::None, OM::_0F, 0x58),
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AvxOpcode::Vaddpd => (LP::_66, OM::_0F, 0x58),
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AvxOpcode::Vsubps => (LP::None, OM::_0F, 0x5C),
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AvxOpcode::Vsubpd => (LP::_66, OM::_0F, 0x5C),
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AvxOpcode::Vmulps => (LP::None, OM::_0F, 0x59),
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AvxOpcode::Vmulpd => (LP::_66, OM::_0F, 0x59),
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AvxOpcode::Vdivps => (LP::None, OM::_0F, 0x5E),
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AvxOpcode::Vdivpd => (LP::_66, OM::_0F, 0x5E),
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AvxOpcode::Vpcmpeqb => (LP::_66, OM::_0F, 0x74),
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AvxOpcode::Vpcmpeqw => (LP::_66, OM::_0F, 0x75),
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AvxOpcode::Vpcmpeqd => (LP::_66, OM::_0F, 0x76),
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AvxOpcode::Vpcmpeqq => (LP::_66, OM::_0F38, 0x29),
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AvxOpcode::Vpcmpgtb => (LP::_66, OM::_0F, 0x64),
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AvxOpcode::Vpcmpgtw => (LP::_66, OM::_0F, 0x65),
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AvxOpcode::Vpcmpgtd => (LP::_66, OM::_0F, 0x66),
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AvxOpcode::Vpcmpgtq => (LP::_66, OM::_0F38, 0x37),
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AvxOpcode::Vmovlhps => (LP::None, OM::_0F, 0x16),
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AvxOpcode::Vpminsb => (LP::_66, OM::_0F38, 0x38),
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AvxOpcode::Vpminsw => (LP::_66, OM::_0F, 0xEA),
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AvxOpcode::Vpminsd => (LP::_66, OM::_0F38, 0x39),
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AvxOpcode::Vpmaxsb => (LP::_66, OM::_0F38, 0x3C),
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AvxOpcode::Vpmaxsw => (LP::_66, OM::_0F, 0xEE),
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AvxOpcode::Vpmaxsd => (LP::_66, OM::_0F38, 0x3D),
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AvxOpcode::Vpminub => (LP::_66, OM::_0F, 0xDA),
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AvxOpcode::Vpminuw => (LP::_66, OM::_0F38, 0x3A),
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AvxOpcode::Vpminud => (LP::_66, OM::_0F38, 0x3B),
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AvxOpcode::Vpmaxub => (LP::_66, OM::_0F, 0xDE),
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AvxOpcode::Vpmaxuw => (LP::_66, OM::_0F38, 0x3E),
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AvxOpcode::Vpmaxud => (LP::_66, OM::_0F38, 0x3F),
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AvxOpcode::Vpunpcklbw => (LP::_66, OM::_0F, 0x60),
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AvxOpcode::Vpunpckhbw => (LP::_66, OM::_0F, 0x68),
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AvxOpcode::Vpacksswb => (LP::_66, OM::_0F, 0x63),
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AvxOpcode::Vpackssdw => (LP::_66, OM::_0F, 0x6B),
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AvxOpcode::Vpackuswb => (LP::_66, OM::_0F, 0x67),
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AvxOpcode::Vpackusdw => (LP::_66, OM::_0F38, 0x2B),
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AvxOpcode::Vpmaddwd => (LP::_66, OM::_0F, 0xF5),
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AvxOpcode::Vpmaddubsw => (LP::_66, OM::_0F38, 0x04),
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AvxOpcode::Vpshufb => (LP::_66, OM::_0F38, 0x00),
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AvxOpcode::Vpsllw => (LP::_66, OM::_0F, 0xF1),
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AvxOpcode::Vpslld => (LP::_66, OM::_0F, 0xF2),
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AvxOpcode::Vpsllq => (LP::_66, OM::_0F, 0xF3),
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AvxOpcode::Vpsraw => (LP::_66, OM::_0F, 0xE1),
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AvxOpcode::Vpsrad => (LP::_66, OM::_0F, 0xE2),
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_ => panic!("unexpected rmir vex opcode {op:?}"),
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};
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VexInstruction::new()
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.length(VexVectorLength::V128)
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.prefix(prefix)
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.map(map)
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.opcode(opcode)
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.map(OpcodeMap::_0F)
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.reg(dst.to_real_reg().unwrap().hw_enc())
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.vvvv(src1.to_real_reg().unwrap().hw_enc())
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.rm(src2)
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@@ -2056,27 +2173,70 @@ pub(crate) fn emit(
|
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} => {
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let dst = allocs.next(dst.to_reg().to_reg());
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let src1 = allocs.next(src1.to_reg());
|
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let src2 = src2.clone().to_reg_mem().with_allocs(allocs);
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|
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let (w, opcode) = match op {
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AvxOpcode::Vcmpps => (false, 0xC2),
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_ => unreachable!(),
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let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
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RegMem::Reg { reg } => {
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RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
|
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}
|
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RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
|
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};
|
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|
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match src2 {
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RegMem::Reg { reg: src } => VexInstruction::new()
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.length(VexVectorLength::V128)
|
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.prefix(LegacyPrefixes::None)
|
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.map(OpcodeMap::_0F)
|
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.w(w)
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.opcode(opcode)
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.reg(dst.to_real_reg().unwrap().hw_enc())
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.rm(src.to_real_reg().unwrap().hw_enc())
|
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.vvvv(src1.to_real_reg().unwrap().hw_enc())
|
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.imm(*imm)
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.encode(sink),
|
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_ => todo!(),
|
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let (w, prefix, map, opcode) = match op {
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AvxOpcode::Vcmpps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC2),
|
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AvxOpcode::Vcmppd => (false, LegacyPrefixes::_66, OpcodeMap::_0F, 0xC2),
|
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AvxOpcode::Vpalignr => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x0F),
|
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AvxOpcode::Vinsertps => (false, LegacyPrefixes::_66, OpcodeMap::_0F3A, 0x21),
|
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AvxOpcode::Vshufps => (false, LegacyPrefixes::None, OpcodeMap::_0F, 0xC6),
|
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_ => panic!("unexpected rmr_imm_vex opcode {op:?}"),
|
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};
|
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|
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VexInstruction::new()
|
||||
.length(VexVectorLength::V128)
|
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.prefix(prefix)
|
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.map(map)
|
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.w(w)
|
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.opcode(opcode)
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.reg(dst.to_real_reg().unwrap().hw_enc())
|
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.vvvv(src1.to_real_reg().unwrap().hw_enc())
|
||||
.rm(src2)
|
||||
.imm(*imm)
|
||||
.encode(sink);
|
||||
}
|
||||
|
||||
Inst::XmmVexPinsr {
|
||||
op,
|
||||
src1,
|
||||
src2,
|
||||
dst,
|
||||
imm,
|
||||
} => {
|
||||
let dst = allocs.next(dst.to_reg().to_reg());
|
||||
let src1 = allocs.next(src1.to_reg());
|
||||
let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
|
||||
RegMem::Reg { reg } => {
|
||||
RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
|
||||
}
|
||||
RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
|
||||
};
|
||||
|
||||
let (w, map, opcode) = match op {
|
||||
AvxOpcode::Vpinsrb => (false, OpcodeMap::_0F3A, 0x20),
|
||||
AvxOpcode::Vpinsrw => (false, OpcodeMap::_0F, 0xC4),
|
||||
AvxOpcode::Vpinsrd => (false, OpcodeMap::_0F3A, 0x22),
|
||||
AvxOpcode::Vpinsrq => (true, OpcodeMap::_0F3A, 0x22),
|
||||
_ => panic!("unexpected vex_pinsr opcode {op:?}"),
|
||||
};
|
||||
|
||||
VexInstruction::new()
|
||||
.length(VexVectorLength::V128)
|
||||
.prefix(LegacyPrefixes::_66)
|
||||
.map(map)
|
||||
.w(w)
|
||||
.opcode(opcode)
|
||||
.reg(dst.to_real_reg().unwrap().hw_enc())
|
||||
.vvvv(src1.to_real_reg().unwrap().hw_enc())
|
||||
.rm(src2)
|
||||
.imm(*imm)
|
||||
.encode(sink);
|
||||
}
|
||||
|
||||
Inst::XmmRmRVex3 {
|
||||
@@ -2092,11 +2252,14 @@ pub(crate) fn emit(
|
||||
let src2 = allocs.next(src2.to_reg());
|
||||
let src3 = src3.clone().to_reg_mem().with_allocs(allocs);
|
||||
|
||||
let (w, opcode) = match op {
|
||||
AvxOpcode::Vfmadd213ss => (false, 0xA9),
|
||||
AvxOpcode::Vfmadd213sd => (true, 0xA9),
|
||||
AvxOpcode::Vfmadd213ps => (false, 0xA8),
|
||||
AvxOpcode::Vfmadd213pd => (true, 0xA8),
|
||||
let (w, map, opcode) = match op {
|
||||
AvxOpcode::Vfmadd213ss => (false, OpcodeMap::_0F38, 0xA9),
|
||||
AvxOpcode::Vfmadd213sd => (true, OpcodeMap::_0F38, 0xA9),
|
||||
AvxOpcode::Vfmadd213ps => (false, OpcodeMap::_0F38, 0xA8),
|
||||
AvxOpcode::Vfmadd213pd => (true, OpcodeMap::_0F38, 0xA8),
|
||||
AvxOpcode::Vblendvps => (false, OpcodeMap::_0F3A, 0x4A),
|
||||
AvxOpcode::Vblendvpd => (false, OpcodeMap::_0F3A, 0x4B),
|
||||
AvxOpcode::Vpblendvb => (false, OpcodeMap::_0F3A, 0x4C),
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
@@ -2104,7 +2267,7 @@ pub(crate) fn emit(
|
||||
RegMem::Reg { reg: src } => VexInstruction::new()
|
||||
.length(VexVectorLength::V128)
|
||||
.prefix(LegacyPrefixes::_66)
|
||||
.map(OpcodeMap::_0F38)
|
||||
.map(map)
|
||||
.w(w)
|
||||
.opcode(opcode)
|
||||
.reg(dst.to_real_reg().unwrap().hw_enc())
|
||||
@@ -2115,6 +2278,42 @@ pub(crate) fn emit(
|
||||
};
|
||||
}
|
||||
|
||||
Inst::XmmRmRBlendVex {
|
||||
op,
|
||||
src1,
|
||||
src2,
|
||||
mask,
|
||||
dst,
|
||||
} => {
|
||||
let dst = allocs.next(dst.to_reg().to_reg());
|
||||
let src1 = allocs.next(src1.to_reg());
|
||||
let src2 = match src2.clone().to_reg_mem().with_allocs(allocs) {
|
||||
RegMem::Reg { reg } => {
|
||||
RegisterOrAmode::Register(reg.to_real_reg().unwrap().hw_enc().into())
|
||||
}
|
||||
RegMem::Mem { addr } => RegisterOrAmode::Amode(addr.finalize(state, sink)),
|
||||
};
|
||||
let mask = allocs.next(mask.to_reg());
|
||||
|
||||
let opcode = match op {
|
||||
AvxOpcode::Vblendvps => 0x4A,
|
||||
AvxOpcode::Vblendvpd => 0x4B,
|
||||
AvxOpcode::Vpblendvb => 0x4C,
|
||||
_ => unreachable!(),
|
||||
};
|
||||
|
||||
VexInstruction::new()
|
||||
.length(VexVectorLength::V128)
|
||||
.prefix(LegacyPrefixes::_66)
|
||||
.map(OpcodeMap::_0F3A)
|
||||
.opcode(opcode)
|
||||
.reg(dst.to_real_reg().unwrap().hw_enc())
|
||||
.vvvv(src1.to_real_reg().unwrap().hw_enc())
|
||||
.rm(src2)
|
||||
.imm(mask.to_real_reg().unwrap().hw_enc() << 4)
|
||||
.encode(sink);
|
||||
}
|
||||
|
||||
Inst::XmmRmREvex {
|
||||
op,
|
||||
src1,
|
||||
@@ -2259,10 +2458,7 @@ pub(crate) fn emit(
|
||||
imm,
|
||||
size,
|
||||
} => {
|
||||
let (src2, dst) = if inst.produces_const() {
|
||||
let dst = allocs.next(dst.to_reg());
|
||||
(RegMem::Reg { reg: dst }, dst)
|
||||
} else if !op.uses_src1() {
|
||||
let (src2, dst) = if !op.uses_src1() {
|
||||
let dst = allocs.next(dst.to_reg());
|
||||
let src2 = src2.with_allocs(allocs);
|
||||
(src2, dst)
|
||||
|
||||
Reference in New Issue
Block a user