s390x: Codegen fixes and preparation for ISLE migration

In preparing the back-end to move to ISLE, I detected a
number of codegen bugs in the existing code, which are
fixed here:

- Fix internal compiler error with uload16/icmp corner case.
- Fix broken Cls lowering.
- Correctly mask shift count for i8/i16 shifts.

In addition, I made several changes to operand encodings
in various MInst patterns.  These should not have any
functional effect, but will make the ISLE migration easier:

- Encode floating-point constants as u32/u64 in MInst patterns.
- Encode shift amounts as u8 and Reg in ShiftOp pattern.
- Use MemArg in LoadMultiple64 and StoreMultiple64 patterns.

cranelift/filetests/filetests/isa/s390x/shift-rotate.clif

@@ -251,10 +251,8 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
-; FIXME: check shift count ?
-
 ; check:  llhr %r2, %r2
-; nextln: nill %r3, 31
+; nextln: nill %r3, 15
 ; nextln: srlk %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -276,7 +274,7 @@ block0(v0: i8, v1: i8):
 }
 
 ; check:  llcr %r2, %r2
-; nextln: nill %r3, 31
+; nextln: nill %r3, 7
 ; nextln: srlk %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -339,7 +337,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
-; check:  nill %r3, 31
+; check:  nill %r3, 15
 ; nextln: sllk %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -359,7 +357,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
-; check:  nill %r3, 31
+; check:  nill %r3, 7
 ; nextln: sllk %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -422,7 +420,7 @@ block0(v0: i16, v1: i16):
 }
 
 ; check:  lhr %r2, %r2
-; nextln: nill %r3, 31
+; nextln: nill %r3, 15
 ; nextln: srak %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -444,7 +442,7 @@ block0(v0: i8, v1: i8):
 }
 
 ; check:  lbr %r2, %r2
-; nextln: nill %r3, 31
+; nextln: nill %r3, 7
 ; nextln: srak %r2, %r2, 0(%r3)
 ; nextln: br %r14