s390x: Codegen fixes and preparation for ISLE migration

In preparing the back-end to move to ISLE, I detected a
number of codegen bugs in the existing code, which are
fixed here:

- Fix internal compiler error with uload16/icmp corner case.
- Fix broken Cls lowering.
- Correctly mask shift count for i8/i16 shifts.

In addition, I made several changes to operand encodings
in various MInst patterns.  These should not have any
functional effect, but will make the ISLE migration easier:

- Encode floating-point constants as u32/u64 in MInst patterns.
- Encode shift amounts as u8 and Reg in ShiftOp pattern.
- Use MemArg in LoadMultiple64 and StoreMultiple64 patterns.

cranelift/filetests/filetests/isa/s390x/bitops.clif

@@ -93,7 +93,7 @@ block0(v0: i64):
 }
 
 ; check:  srag %r3, %r2, 63
-; nextln: xgr %r3, %r2
+; nextln: xgrk %r2, %r3, %r2
 ; nextln: flogr %r0, %r2
 ; nextln: lgr %r2, %r0
 ; nextln: br %r14
@@ -106,7 +106,7 @@ block0(v0: i32):
 
 ; check:  lgfr %r2, %r2
 ; nextln: srag %r3, %r2, 63
-; nextln: xgr %r3, %r2
+; nextln: xgrk %r2, %r3, %r2
 ; nextln: flogr %r0, %r2
 ; nextln: lr %r2, %r0
 ; nextln: ahi %r2, -32
@@ -120,7 +120,7 @@ block0(v0: i16):
 
 ; check:  lghr %r2, %r2
 ; nextln: srag %r3, %r2, 63
-; nextln: xgr %r3, %r2
+; nextln: xgrk %r2, %r3, %r2
 ; nextln: flogr %r0, %r2
 ; nextln: lr %r2, %r0
 ; nextln: ahi %r2, -48
@@ -134,7 +134,7 @@ block0(v0: i8):
 
 ; check:  lgbr %r2, %r2
 ; nextln: srag %r3, %r2, 63
-; nextln: xgr %r3, %r2
+; nextln: xgrk %r2, %r3, %r2
 ; nextln: flogr %r0, %r2
 ; nextln: lr %r2, %r0
 ; nextln: ahi %r2, -56

cranelift/filetests/filetests/isa/s390x/icmp.clif

@@ -418,6 +418,19 @@ block0(v0: i64):
 ; nextln: lochil %r2, 1
 ; nextln: br %r14
 
+function %icmp_ult_i64_mem_ext16(i64, i64) -> b1 {
+block0(v0: i64, v1: i64):
+  v2 = uload16.i64 v1
+  v3 = icmp.i64 ult v0, v2
+  return v3
+}
+
+; check:  llgh %r3, 0(%r3)
+; check:  clgr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
 function %icmp_ult_i64_sym_ext16(i64) -> b1 {
   gv0 = symbol colocated %sym
 block0(v0: i64):
@@ -493,6 +506,19 @@ block0(v0: i32):
 ; nextln: lochil %r2, 1
 ; nextln: br %r14
 
+function %icmp_ult_i32_mem_ext16(i32, i64) -> b1 {
+block0(v0: i32, v1: i64):
+  v2 = uload16.i32 v1
+  v3 = icmp.i32 ult v0, v2
+  return v3
+}
+
+; check:  llh %r3, 0(%r3)
+; check:  clr %r2, %r3
+; nextln: lhi %r2, 0
+; nextln: lochil %r2, 1
+; nextln: br %r14
+
 function %icmp_ult_i32_sym_ext16(i32) -> b1 {
   gv0 = symbol colocated %sym
 block0(v0: i32):

cranelift/filetests/filetests/isa/s390x/shift-rotate.clif

@@ -251,10 +251,8 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
-; FIXME: check shift count ?
-
 ; check:  llhr %r2, %r2
-; nextln: nill %r3, 31
+; nextln: nill %r3, 15
 ; nextln: srlk %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -276,7 +274,7 @@ block0(v0: i8, v1: i8):
 }
 
 ; check:  llcr %r2, %r2
-; nextln: nill %r3, 31
+; nextln: nill %r3, 7
 ; nextln: srlk %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -339,7 +337,7 @@ block0(v0: i16, v1: i16):
   return v2
 }
 
-; check:  nill %r3, 31
+; check:  nill %r3, 15
 ; nextln: sllk %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -359,7 +357,7 @@ block0(v0: i8, v1: i8):
   return v2
 }
 
-; check:  nill %r3, 31
+; check:  nill %r3, 7
 ; nextln: sllk %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -422,7 +420,7 @@ block0(v0: i16, v1: i16):
 }
 
 ; check:  lhr %r2, %r2
-; nextln: nill %r3, 31
+; nextln: nill %r3, 15
 ; nextln: srak %r2, %r2, 0(%r3)
 ; nextln: br %r14
 
@@ -444,7 +442,7 @@ block0(v0: i8, v1: i8):
 }
 
 ; check:  lbr %r2, %r2
-; nextln: nill %r3, 31
+; nextln: nill %r3, 7
 ; nextln: srak %r2, %r2, 0(%r3)
 ; nextln: br %r14