Enable and fix several more clippy lints.

This commit is contained in:
Dan Gohman
2018-04-02 08:48:06 -07:00
parent 5c6cb202d8
commit bf597b7abf
71 changed files with 360 additions and 219 deletions

View File

@@ -47,7 +47,7 @@ def gen_formats(fmt):
with fmt.indented(
"impl<'a> From<&'a InstructionData> for InstructionFormat {", '}'):
with fmt.indented(
"fn from(inst: &'a InstructionData) -> InstructionFormat {",
"fn from(inst: &'a InstructionData) -> Self {",
'}'):
m = srcgen.Match('*inst')
for f in InstructionFormat.all_formats:

View File

@@ -29,7 +29,7 @@ def gen_enum_types(sgrp, fmt):
continue
ty = camel_case(setting.name)
fmt.doc_comment('Values for `{}`.'.format(setting))
fmt.line('#[derive(Debug, PartialEq, Eq)]')
fmt.line('#[derive(Debug, Copy, Clone, PartialEq, Eq)]')
with fmt.indented('pub enum {} {{'.format(ty), '}'):
for v in setting.values:
fmt.doc_comment('`{}`.'.format(v))
@@ -223,7 +223,7 @@ def gen_display(sgrp, fmt):
fmt.line(
'TEMPLATE.format_toml_value(d.detail,' +
'self.bytes[d.offset as usize], f)?;')
fmt.line('writeln!(f, "")?;')
fmt.line('writeln!(f)?;')
fmt.line('Ok(())')
@@ -241,7 +241,7 @@ def gen_constructor(sgrp, parent, fmt):
fmt.doc_comment('Create flags {} settings group.'.format(sgrp.name))
fmt.line('#[allow(unused_variables)]')
with fmt.indented(
'pub fn new({}) -> Flags {{'.format(args), '}'):
'pub fn new({}) -> Self {{'.format(args), '}'):
fmt.line('let bvec = builder.state_for("{}");'.format(sgrp.name))
fmt.line('let mut bytes = [0; {}];'.format(sgrp.byte_size()))
fmt.line(
@@ -252,12 +252,12 @@ def gen_constructor(sgrp, parent, fmt):
# Stop here without predicates.
if len(sgrp.predicate_number) == sgrp.boolean_settings:
fmt.line('Flags { bytes: bytes }')
fmt.line('Self { bytes }')
return
# Now compute the predicates.
fmt.line(
'let mut {} = Flags {{ bytes: bytes }};'
'let mut {} = Self {{ bytes }};'
.format(sgrp.name))
for pred, number in sgrp.predicate_number.items():

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@@ -530,7 +530,7 @@ puid_bool = TailRecipe(
// The destination register is encoded in the low bits of the opcode.
// No ModR/M.
PUT_OP(bits | (out_reg0 & 7), rex1(out_reg0), sink);
let imm: u32 = if imm.into() { 1 } else { 0 };
let imm: u32 = if imm { 1 } else { 0 };
sink.put4(imm);
''')