Use new regalloc.rs version with dense vreg->rreg maps.

This PR updates Cranelift to use the new version of regalloc.rs
(bytecodealliance/regalloc.rs#55) that provides dense vreg->rreg maps to
the `map_reg()` function for each instruction, rather than the earlier
hashmap-based approach.

In one test (regex-rs.wasm), this PR results in a 15% reduction in
memory allocations (1245MB -> 1060MB) as measured by DHAT on `clif-util
wasm` runs.

cranelift/codegen/src/machinst/mod.rs

@@ -105,9 +105,10 @@ use crate::settings::Flags;
 use alloc::boxed::Box;
 use alloc::vec::Vec;
 use core::fmt::Debug;
-use regalloc::Map as RegallocMap;
 use regalloc::RegUsageCollector;
-use regalloc::{RealReg, RealRegUniverse, Reg, RegClass, SpillSlot, VirtualReg, Writable};
+use regalloc::{
+    RealReg, RealRegUniverse, Reg, RegClass, RegUsageMapper, SpillSlot, VirtualReg, Writable,
+};
 use std::string::String;
 use target_lexicon::Triple;
 
@@ -136,11 +137,7 @@ pub trait MachInst: Clone + Debug {
 
     /// Map virtual registers to physical registers using the given virt->phys
     /// maps corresponding to the program points prior to, and after, this instruction.
-    fn map_regs(
-        &mut self,
-        pre_map: &RegallocMap<VirtualReg, RealReg>,
-        post_map: &RegallocMap<VirtualReg, RealReg>,
-    );
+    fn map_regs(&mut self, maps: &RegUsageMapper);
 
     /// If this is a simple move, return the (source, destination) tuple of registers.
     fn is_move(&self) -> Option<(Writable<Reg>, Reg)>;

cranelift/codegen/src/machinst/vcode.rs

@@ -25,7 +25,9 @@ use crate::settings;
 
 use regalloc::Function as RegallocFunction;
 use regalloc::Set as RegallocSet;
-use regalloc::{BlockIx, InstIx, Range, RegAllocResult, RegClass, RegUsageCollector};
+use regalloc::{
+    BlockIx, InstIx, Range, RegAllocResult, RegClass, RegUsageCollector, RegUsageMapper,
+};
 
 use alloc::boxed::Box;
 use alloc::vec::Vec;
@@ -647,18 +649,18 @@ impl<I: VCodeInst> RegallocFunction for VCode<I> {
         insn.get_regs(collector)
     }
 
-    fn map_regs(
-        insn: &mut I,
-        pre_map: &RegallocMap<VirtualReg, RealReg>,
-        post_map: &RegallocMap<VirtualReg, RealReg>,
-    ) {
-        insn.map_regs(pre_map, post_map);
+    fn map_regs(insn: &mut I, mapper: &RegUsageMapper) {
+        insn.map_regs(mapper);
     }
 
     fn is_move(&self, insn: &I) -> Option<(Writable<Reg>, Reg)> {
         insn.is_move()
     }
 
+    fn get_vreg_count_estimate(&self) -> Option<usize> {
+        Some(self.vreg_types.len())
+    }
+
     fn get_spillslot_size(&self, regclass: RegClass, vreg: VirtualReg) -> u32 {
         let ty = self.vreg_type(vreg);
         self.abi.get_spillslot_size(regclass, ty)