s390x: Enable object backend (#4680)

This enables the object backend for s390x, in particular the
processing of all required relocations.

This uncovered a bug: we need to use PLT relocations for the
target of calls, which we currently do not.  Fixed by adding
a new S390xPLTRel32Dbl reloc type and using it where needed.

cranelift/codegen/src/binemit/mod.rs

@@ -43,6 +43,8 @@ pub enum Reloc {
     Arm64Call,
     /// s390x PC-relative 4-byte offset
     S390xPCRel32Dbl,
+    /// s390x PC-relative 4-byte offset to PLT
+    S390xPLTRel32Dbl,
 
     /// Elf x86_64 32 bit signed PC relative offset to two GOT entries for GD symbol.
     ElfX86_64TlsGd,
@@ -74,6 +76,7 @@ impl fmt::Display for Reloc {
             Self::Abs4 => write!(f, "Abs4"),
             Self::Abs8 => write!(f, "Abs8"),
             Self::S390xPCRel32Dbl => write!(f, "PCRel32Dbl"),
+            Self::S390xPLTRel32Dbl => write!(f, "PLTRel32Dbl"),
             Self::X86PCRel4 => write!(f, "PCRel4"),
             Self::X86CallPCRel4 => write!(f, "CallPCRel4"),
             Self::X86CallPLTRel4 => write!(f, "CallPLTRel4"),

cranelift/codegen/src/isa/s390x/inst/emit.rs

@@ -3216,7 +3216,7 @@ impl MachInstEmit for Inst {
                 }
 
                 let opcode = 0xc05; // BRASL
-                let reloc = Reloc::S390xPCRel32Dbl;
+                let reloc = Reloc::S390xPLTRel32Dbl;
                 if let Some(s) = state.take_stack_map() {
                     sink.add_stack_map(StackMapExtent::UpcomingBytes(6), s);
                 }

cranelift/codegen/src/isa/s390x/inst/mod.rs

@@ -3077,6 +3077,7 @@ impl MachInstLabelUse for LabelUse {
     fn from_reloc(reloc: Reloc, addend: Addend) -> Option<Self> {
         match (reloc, addend) {
             (Reloc::S390xPCRel32Dbl, 2) => Some(LabelUse::PCRel32Dbl),
+            (Reloc::S390xPLTRel32Dbl, 2) => Some(LabelUse::PCRel32Dbl),
             _ => None,
         }
     }