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machinst x64: lower binary ALU operators;

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This commit is contained in:
Benjamin Bouvier
2020-06-25 18:03:39 +02:00
parent faeed3c7a4
commit bd88065571
1 changed files with 9 additions and 5 deletions
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14
cranelift/codegen/src/isa/x64/lower.rs
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@@ -179,7 +179,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) -> Codeg
} }
} }
Opcode::Iadd | Opcode::Isub => { Opcode::Iadd | Opcode::Isub | Opcode::Imul | Opcode::Band | Opcode::Bor | Opcode::Bxor => {
let lhs = input_to_reg(ctx, inputs[0]); let lhs = input_to_reg(ctx, inputs[0]);
let rhs = input_to_reg_mem_imm(ctx, inputs[1]); let rhs = input_to_reg_mem_imm(ctx, inputs[1]);
let dst = output_to_reg(ctx, outputs[0]); let dst = output_to_reg(ctx, outputs[0]);
@@ -187,10 +187,14 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(ctx: &mut C, insn: IRInst) -> Codeg
// TODO For add, try to commute the operands if one is an immediate. // TODO For add, try to commute the operands if one is an immediate.
let is_64 = int_ty_is_64(ty.unwrap()); let is_64 = int_ty_is_64(ty.unwrap());
let alu_op = if op == Opcode::Iadd { let alu_op = match op {
AluRmiROpcode::Add Opcode::Iadd => AluRmiROpcode::Add,
} else { Opcode::Isub => AluRmiROpcode::Sub,
AluRmiROpcode::Sub Opcode::Imul => AluRmiROpcode::Mul,
Opcode::Band => AluRmiROpcode::And,
Opcode::Bor => AluRmiROpcode::Or,
Opcode::Bxor => AluRmiROpcode::Xor,
_ => unreachable!(),
}; };
ctx.emit(Inst::mov_r_r(true, lhs, dst)); ctx.emit(Inst::mov_r_r(true, lhs, dst));