Encodings for load/store instructions.
We don't support the full set of Intel addressing modes yet. So far we have: - Register indirect, no displacement. - Register indirect, 8-bit signed displacement. - Register indirect, 32-bit signed displacement. The SIB addressing modes will need new Cretonne instruction formats to represent.
This commit is contained in:
Jakob Stoklund Olesen
@@ -92,5 +92,110 @@ ebb0:
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; asm: xorl $1000000, %esi
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[-,%rsi] v47 = bxor_imm v2, 1000000 ; bin: 81 f6 000f4240
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; Load/Store instructions.
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; Register indirect addressing with no displacement.
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; asm: movl %ecx, (%esi)
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store v1, v2 ; bin: 89 0e
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; asm: movl %esi, (%ecx)
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store v2, v1 ; bin: 89 31
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; asm: movw %cx, (%esi)
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istore16 v1, v2 ; bin: 66 89 0e
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; asm: movw %si, (%ecx)
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istore16 v2, v1 ; bin: 66 89 31
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; asm: movb %cl, (%esi)
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istore8 v1, v2 ; bin: 88 0e
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; Can't store %sil in 32-bit mode (needs REX prefix).
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; asm: movl (%ecx), %edi
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[-,%rdi] v100 = load.i32 v1 ; bin: 8b 39
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; asm: movl (%esi), %edx
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[-,%rdx] v101 = load.i32 v2 ; bin: 8b 16
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; asm: movzwl (%ecx), %edi
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[-,%rdi] v102 = uload16.i32 v1 ; bin: 0f b7 39
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; asm: movzwl (%esi), %edx
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[-,%rdx] v103 = uload16.i32 v2 ; bin: 0f b7 16
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; asm: movswl (%ecx), %edi
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[-,%rdi] v104 = sload16.i32 v1 ; bin: 0f bf 39
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; asm: movswl (%esi), %edx
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[-,%rdx] v105 = sload16.i32 v2 ; bin: 0f bf 16
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; asm: movzbl (%ecx), %edi
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[-,%rdi] v106 = uload8.i32 v1 ; bin: 0f b6 39
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; asm: movzbl (%esi), %edx
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[-,%rdx] v107 = uload8.i32 v2 ; bin: 0f b6 16
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; asm: movsbl (%ecx), %edi
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[-,%rdi] v108 = sload8.i32 v1 ; bin: 0f be 39
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; asm: movsbl (%esi), %edx
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[-,%rdx] v109 = sload8.i32 v2 ; bin: 0f be 16
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; Register-indirect with 8-bit signed displacement.
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; asm: movl %ecx, 100(%esi)
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store v1, v2+100 ; bin: 89 4e 64
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; asm: movl %esi, -100(%ecx)
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store v2, v1-100 ; bin: 89 71 9c
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; asm: movw %cx, 100(%esi)
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istore16 v1, v2+100 ; bin: 66 89 4e 64
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; asm: movw %si, -100(%ecx)
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istore16 v2, v1-100 ; bin: 66 89 71 9c
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; asm: movb %cl, 100(%esi)
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istore8 v1, v2+100 ; bin: 88 4e 64
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; asm: movl 50(%ecx), %edi
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[-,%rdi] v110 = load.i32 v1+50 ; bin: 8b 79 32
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; asm: movl -50(%esi), %edx
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[-,%rdx] v111 = load.i32 v2-50 ; bin: 8b 56 ce
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; asm: movzwl 50(%ecx), %edi
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[-,%rdi] v112 = uload16.i32 v1+50 ; bin: 0f b7 79 32
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; asm: movzwl -50(%esi), %edx
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[-,%rdx] v113 = uload16.i32 v2-50 ; bin: 0f b7 56 ce
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; asm: movswl 50(%ecx), %edi
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[-,%rdi] v114 = sload16.i32 v1+50 ; bin: 0f bf 79 32
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; asm: movswl -50(%esi), %edx
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[-,%rdx] v115 = sload16.i32 v2-50 ; bin: 0f bf 56 ce
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; asm: movzbl 50(%ecx), %edi
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[-,%rdi] v116 = uload8.i32 v1+50 ; bin: 0f b6 79 32
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; asm: movzbl -50(%esi), %edx
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[-,%rdx] v117 = uload8.i32 v2-50 ; bin: 0f b6 56 ce
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; asm: movsbl 50(%ecx), %edi
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[-,%rdi] v118 = sload8.i32 v1+50 ; bin: 0f be 79 32
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; asm: movsbl -50(%esi), %edx
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[-,%rdx] v119 = sload8.i32 v2-50 ; bin: 0f be 56 ce
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; Register-indirect with 32-bit signed displacement.
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; asm: movl %ecx, 10000(%esi)
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store v1, v2+10000 ; bin: 89 8e 00002710
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; asm: movl %esi, -10000(%ecx)
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store v2, v1-10000 ; bin: 89 b1 ffffd8f0
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; asm: movw %cx, 10000(%esi)
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istore16 v1, v2+10000 ; bin: 66 89 8e 00002710
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; asm: movw %si, -10000(%ecx)
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istore16 v2, v1-10000 ; bin: 66 89 b1 ffffd8f0
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; asm: movb %cl, 10000(%esi)
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istore8 v1, v2+10000 ; bin: 88 8e 00002710
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; asm: movl 50000(%ecx), %edi
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[-,%rdi] v120 = load.i32 v1+50000 ; bin: 8b b9 0000c350
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; asm: movl -50000(%esi), %edx
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[-,%rdx] v121 = load.i32 v2-50000 ; bin: 8b 96 ffff3cb0
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; asm: movzwl 50000(%ecx), %edi
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[-,%rdi] v122 = uload16.i32 v1+50000 ; bin: 0f b7 b9 0000c350
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; asm: movzwl -50000(%esi), %edx
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[-,%rdx] v123 = uload16.i32 v2-50000 ; bin: 0f b7 96 ffff3cb0
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; asm: movswl 50000(%ecx), %edi
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[-,%rdi] v124 = sload16.i32 v1+50000 ; bin: 0f bf b9 0000c350
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; asm: movswl -50000(%esi), %edx
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[-,%rdx] v125 = sload16.i32 v2-50000 ; bin: 0f bf 96 ffff3cb0
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; asm: movzbl 50000(%ecx), %edi
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[-,%rdi] v126 = uload8.i32 v1+50000 ; bin: 0f b6 b9 0000c350
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; asm: movzbl -50000(%esi), %edx
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[-,%rdx] v127 = uload8.i32 v2-50000 ; bin: 0f b6 96 ffff3cb0
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; asm: movsbl 50000(%ecx), %edi
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[-,%rdi] v128 = sload8.i32 v1+50000 ; bin: 0f be b9 0000c350
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; asm: movsbl -50000(%esi), %edx
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[-,%rdx] v129 = sload8.i32 v2-50000 ; bin: 0f be 96 ffff3cb0
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return
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}
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@@ -4,15 +4,15 @@ Intel Encodings.
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from __future__ import absolute_import
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from base import instructions as base
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from .defs import I32
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from .recipes import Op1rr, Op1rc, Op1rib, Op1rid
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from .recipes import OP
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from . import recipes as rcp
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from .recipes import OP, OP0F, MP66
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I32.enc(base.iadd.i32, Op1rr, OP(0x01))
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I32.enc(base.isub.i32, Op1rr, OP(0x29))
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I32.enc(base.iadd.i32, rcp.Op1rr, OP(0x01))
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I32.enc(base.isub.i32, rcp.Op1rr, OP(0x29))
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I32.enc(base.band.i32, Op1rr, OP(0x21))
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I32.enc(base.bor.i32, Op1rr, OP(0x09))
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I32.enc(base.bxor.i32, Op1rr, OP(0x31))
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I32.enc(base.band.i32, rcp.Op1rr, OP(0x21))
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I32.enc(base.bor.i32, rcp.Op1rr, OP(0x09))
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I32.enc(base.bxor.i32, rcp.Op1rr, OP(0x31))
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# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
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for inst, r in [
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@@ -20,12 +20,45 @@ for inst, r in [
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(base.band_imm.i32, 4),
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(base.bor_imm.i32, 1),
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(base.bxor_imm.i32, 6)]:
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I32.enc(inst, Op1rib, OP(0x83, rrr=r))
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I32.enc(inst, Op1rid, OP(0x81, rrr=r))
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I32.enc(inst, rcp.Op1rib, OP(0x83, rrr=r))
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I32.enc(inst, rcp.Op1rid, OP(0x81, rrr=r))
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# 32-bit shifts and rotates.
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# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
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# and 16-bit shifts would need explicit masking.
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I32.enc(base.ishl.i32.i32, Op1rc, OP(0xd3, rrr=4))
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I32.enc(base.ushr.i32.i32, Op1rc, OP(0xd3, rrr=5))
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I32.enc(base.sshr.i32.i32, Op1rc, OP(0xd3, rrr=7))
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I32.enc(base.ishl.i32.i32, rcp.Op1rc, OP(0xd3, rrr=4))
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I32.enc(base.ushr.i32.i32, rcp.Op1rc, OP(0xd3, rrr=5))
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I32.enc(base.sshr.i32.i32, rcp.Op1rc, OP(0xd3, rrr=7))
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# Loads and stores.
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I32.enc(base.store.i32.i32, rcp.Op1st, OP(0x89))
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I32.enc(base.store.i32.i32, rcp.Op1stDisp8, OP(0x89))
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I32.enc(base.store.i32.i32, rcp.Op1stDisp32, OP(0x89))
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I32.enc(base.istore16.i32.i32, rcp.Mp1st, MP66(0x89))
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I32.enc(base.istore16.i32.i32, rcp.Mp1stDisp8, MP66(0x89))
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I32.enc(base.istore16.i32.i32, rcp.Mp1stDisp32, MP66(0x89))
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I32.enc(base.istore8.i32.i32, rcp.Op1st_abcd, OP(0x88))
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I32.enc(base.istore8.i32.i32, rcp.Op1stDisp8_abcd, OP(0x88))
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I32.enc(base.istore8.i32.i32, rcp.Op1stDisp32_abcd, OP(0x88))
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I32.enc(base.load.i32.i32, rcp.Op1ld, OP(0x8b))
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I32.enc(base.load.i32.i32, rcp.Op1ldDisp8, OP(0x8b))
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I32.enc(base.load.i32.i32, rcp.Op1ldDisp32, OP(0x8b))
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I32.enc(base.uload16.i32.i32, rcp.Op2ld, OP0F(0xb7))
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I32.enc(base.uload16.i32.i32, rcp.Op2ldDisp8, OP0F(0xb7))
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I32.enc(base.uload16.i32.i32, rcp.Op2ldDisp32, OP0F(0xb7))
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I32.enc(base.sload16.i32.i32, rcp.Op2ld, OP0F(0xbf))
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I32.enc(base.sload16.i32.i32, rcp.Op2ldDisp8, OP0F(0xbf))
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I32.enc(base.sload16.i32.i32, rcp.Op2ldDisp32, OP0F(0xbf))
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I32.enc(base.uload8.i32.i32, rcp.Op2ld, OP0F(0xb6))
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I32.enc(base.uload8.i32.i32, rcp.Op2ldDisp8, OP0F(0xb6))
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I32.enc(base.uload8.i32.i32, rcp.Op2ldDisp32, OP0F(0xb6))
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I32.enc(base.sload8.i32.i32, rcp.Op2ld, OP0F(0xbe))
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I32.enc(base.sload8.i32.i32, rcp.Op2ldDisp8, OP0F(0xbe))
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I32.enc(base.sload8.i32.i32, rcp.Op2ldDisp32, OP0F(0xbe))
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@@ -3,9 +3,9 @@ Intel Encoding recipes.
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"""
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from __future__ import absolute_import
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from cdsl.isa import EncRecipe
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from cdsl.predicates import IsSignedInt
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from base.formats import Binary, BinaryImm
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from .registers import GPR
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from cdsl.predicates import IsSignedInt, IsEqual
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from base.formats import Binary, BinaryImm, Store, Load
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from .registers import GPR, ABCD
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# Opcode representation.
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#
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@@ -15,21 +15,21 @@ from .registers import GPR
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# name prefix:
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#
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# <op> Op1* OP(op)
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# 0F <op> Op2* OP(op)
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# 0F <op> Op2* OP0F(op)
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# 0F 38 <op> Op3* OP38(op)
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# 0F 3A <op> Op3* OP3A(op)
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# 66 <op> Mp1* MP66(op)
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# 66 0F <op> Mp2* MP66(op)
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# 66 0F 38 <op> Mp3* MP6638(op)
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# 66 0F 3A <op> Mp3* MP663A(op)
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# 66 0F <op> Mp2* MP660F(op)
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# 66 0F 38 <op> Mp3* MP660F38(op)
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# 66 0F 3A <op> Mp3* MP660F3A(op)
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# F2 <op> Mp1* MPF2(op)
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# F2 0F <op> Mp2* MPF2(op)
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# F2 0F 38 <op> Mp3* MPF238(op)
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# F2 0F 3A <op> Mp3* MPF23A(op)
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# F2 0F <op> Mp2* MPF20F(op)
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# F2 0F 38 <op> Mp3* MPF20F38(op)
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# F2 0F 3A <op> Mp3* MPF20F3A(op)
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# F3 <op> Mp1* MPF3(op)
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# F3 0F <op> Mp2* MPF3(op)
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# F3 0F 38 <op> Mp3* MPF338(op)
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# F3 0F 3A <op> Mp3* MPF33A(op)
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# F3 0F <op> Mp2* MP0FF3(op)
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# F3 0F 38 <op> Mp3* MPF30F38(op)
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# F3 0F 3A <op> Mp3* MPF30F3A(op)
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#
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# VEX/XOP and EVEX prefixes are not yet supported.
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#
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@@ -63,6 +63,16 @@ def OP(op, pp=0, mm=0, rrr=0, w=0):
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return op | (pp << 8) | (mm << 10) | (rrr << 12) | (w << 15)
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def OP0F(op, rrr=0, w=0):
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# type: (int, int, int) -> int
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return OP(op, pp=0, mm=1, rrr=rrr, w=w)
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def MP66(op, rrr=0, w=0):
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# type: (int, int, int) -> int
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return OP(op, pp=1, mm=0, rrr=rrr, w=w)
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# XX /r
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Op1rr = EncRecipe('Op1rr', Binary, size=2, ins=(GPR, GPR), outs=0)
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@@ -78,3 +88,78 @@ Op1rib = EncRecipe(
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Op1rid = EncRecipe(
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'Op1rid', BinaryImm, size=6, ins=GPR, outs=0,
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instp=IsSignedInt(BinaryImm.imm, 32))
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#
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# Store recipes.
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#
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# XX /r register-indirect store with no offset.
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Op1st = EncRecipe(
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'Op1st', Store, size=2, ins=(GPR, GPR), outs=(),
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instp=IsEqual(Store.offset, 0))
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# XX /r register-indirect store with no offset.
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# Only ABCD allowed for stored value. This is for byte stores.
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Op1st_abcd = EncRecipe(
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'Op1st_abcd', Store, size=2, ins=(ABCD, GPR), outs=(),
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instp=IsEqual(Store.offset, 0))
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# XX /r register-indirect store with 8-bit offset.
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Op1stDisp8 = EncRecipe(
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'Op1stDisp8', Store, size=3, ins=(GPR, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8))
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Op1stDisp8_abcd = EncRecipe(
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'Op1stDisp8_abcd', Store, size=3, ins=(ABCD, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8))
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# XX /r register-indirect store with 32-bit offset.
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Op1stDisp32 = EncRecipe('Op1stDisp32', Store, size=6, ins=(GPR, GPR), outs=())
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Op1stDisp32_abcd = EncRecipe(
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'Op1stDisp32_abcd', Store, size=6, ins=(ABCD, GPR), outs=())
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# PP WW /r register-indirect store with no offset.
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Mp1st = EncRecipe(
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'Mp1st', Store, size=3, ins=(GPR, GPR), outs=(),
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instp=IsEqual(Store.offset, 0))
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# PP XX /r register-indirect store with 8-bit offset.
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Mp1stDisp8 = EncRecipe(
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'Mp1stDisp8', Store, size=4, ins=(GPR, GPR), outs=(),
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instp=IsSignedInt(Store.offset, 8))
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# PP XX /r register-indirect store with 32-bit offset.
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Mp1stDisp32 = EncRecipe('Mp1stDisp32', Store, size=7, ins=(GPR, GPR), outs=())
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#
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# Load recipes
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#
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# XX /r load with no offset.
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Op1ld = EncRecipe(
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'Op1ld', Load, size=2, ins=(GPR), outs=(GPR),
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instp=IsEqual(Load.offset, 0))
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# XX /r load with 8-bit offset.
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Op1ldDisp8 = EncRecipe(
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'Op1ldDisp8', Load, size=3, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 8))
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# XX /r load with 32-bit offset.
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Op1ldDisp32 = EncRecipe(
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'Op1ldDisp32', Load, size=6, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 32))
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# 0F XX /r load with no offset.
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Op2ld = EncRecipe(
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'Op2ld', Load, size=3, ins=(GPR), outs=(GPR),
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instp=IsEqual(Load.offset, 0))
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# XX /r load with 8-bit offset.
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Op2ldDisp8 = EncRecipe(
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'Op2ldDisp8', Load, size=4, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 8))
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# XX /r load with 32-bit offset.
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Op2ldDisp32 = EncRecipe(
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'Op2ldDisp32', Load, size=7, ins=(GPR), outs=(GPR),
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instp=IsSignedInt(Load.offset, 32))
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@@ -8,11 +8,30 @@ include!(concat!(env!("OUT_DIR"), "/binemit-intel.rs"));
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pub static RELOC_NAMES: [&'static str; 1] = ["Call"];
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// Emit single-byte opcode.
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fn put_op1<CS: CodeSink + ?Sized>(bits: u16, sink: &mut CS) {
|
||||
debug_assert!(bits & 0x0f00 == 0, "Invalid encoding bits for Op1*");
|
||||
sink.put1(bits as u8);
|
||||
}
|
||||
|
||||
// Emit two-byte opcode: 0F XX
|
||||
fn put_op2<CS: CodeSink + ?Sized>(bits: u16, sink: &mut CS) {
|
||||
debug_assert!(bits & 0x0f00 == 0x0400, "Invalid encoding bits for Op2*");
|
||||
sink.put1(0x0f);
|
||||
sink.put1(bits as u8);
|
||||
}
|
||||
|
||||
// Mandatory prefix bytes for Mp* opcodes.
|
||||
const PREFIX: [u8; 3] = [0x66, 0xf3, 0xf2];
|
||||
|
||||
// Emit single-byte opcode with mandatory prefix.
|
||||
fn put_mp1<CS: CodeSink + ?Sized>(bits: u16, sink: &mut CS) {
|
||||
debug_assert!(bits & 0x0c00 == 0, "Invalid encoding bits for Mp1*");
|
||||
let pp = (bits >> 8) & 3;
|
||||
sink.put1(PREFIX[(pp - 1) as usize]);
|
||||
sink.put1(bits as u8);
|
||||
}
|
||||
|
||||
/// Emit a ModR/M byte for reg-reg operands.
|
||||
fn modrm_rr<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
|
||||
let reg = reg as u8 & 7;
|
||||
@@ -33,6 +52,42 @@ fn modrm_r_bits<CS: CodeSink + ?Sized>(rm: RegUnit, bits: u16, sink: &mut CS) {
|
||||
sink.put1(b);
|
||||
}
|
||||
|
||||
/// Emit a mode 00 ModR/M byte. This is a register-indirect addressing mode with no offset.
|
||||
/// Registers %rsp and %rbp are invalid for `rm`, %rsp indicates a SIB byte, and %rbp indicates an
|
||||
/// absolute immediate 32-bit address.
|
||||
fn modrm_rm<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
|
||||
let reg = reg as u8 & 7;
|
||||
let rm = rm as u8 & 7;
|
||||
let mut b = 0b00000000;
|
||||
b |= reg << 3;
|
||||
b |= rm;
|
||||
sink.put1(b);
|
||||
}
|
||||
|
||||
/// Emit a mode 01 ModR/M byte. This is a register-indirect addressing mode with 8-bit
|
||||
/// displacement.
|
||||
/// Register %rsp is invalid for `rm`. It indicates the presence of a SIB byte.
|
||||
fn modrm_disp8<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
|
||||
let reg = reg as u8 & 7;
|
||||
let rm = rm as u8 & 7;
|
||||
let mut b = 0b01000000;
|
||||
b |= reg << 3;
|
||||
b |= rm;
|
||||
sink.put1(b);
|
||||
}
|
||||
|
||||
/// Emit a mode 10 ModR/M byte. This is a register-indirect addressing mode with 32-bit
|
||||
/// displacement.
|
||||
/// Register %rsp is invalid for `rm`. It indicates the presence of a SIB byte.
|
||||
fn modrm_disp32<CS: CodeSink + ?Sized>(rm: RegUnit, reg: RegUnit, sink: &mut CS) {
|
||||
let reg = reg as u8 & 7;
|
||||
let rm = rm as u8 & 7;
|
||||
let mut b = 0b10000000;
|
||||
b |= reg << 3;
|
||||
b |= rm;
|
||||
sink.put1(b);
|
||||
}
|
||||
|
||||
fn recipe_op1rr<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Binary { args, .. } = func.dfg[inst] {
|
||||
put_op1(func.encodings[inst].bits(), sink);
|
||||
@@ -77,3 +132,168 @@ fn recipe_op1rid<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut
|
||||
panic!("Expected BinaryImm format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
// Store recipes.
|
||||
|
||||
fn recipe_op1st<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Store { args, .. } = func.dfg[inst] {
|
||||
put_op1(func.encodings[inst].bits(), sink);
|
||||
modrm_rm(func.locations[args[1]].unwrap_reg(),
|
||||
func.locations[args[0]].unwrap_reg(),
|
||||
sink);
|
||||
} else {
|
||||
panic!("Expected Store format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
// This is just a tighter register class constraint.
|
||||
fn recipe_op1st_abcd<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
recipe_op1st(func, inst, sink)
|
||||
}
|
||||
|
||||
fn recipe_mp1st<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Store { args, .. } = func.dfg[inst] {
|
||||
put_mp1(func.encodings[inst].bits(), sink);
|
||||
modrm_rm(func.locations[args[1]].unwrap_reg(),
|
||||
func.locations[args[0]].unwrap_reg(),
|
||||
sink);
|
||||
} else {
|
||||
panic!("Expected Store format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op1stdisp8<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Store { args, offset, .. } = func.dfg[inst] {
|
||||
put_op1(func.encodings[inst].bits(), sink);
|
||||
modrm_disp8(func.locations[args[1]].unwrap_reg(),
|
||||
func.locations[args[0]].unwrap_reg(),
|
||||
sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put1(offset as u8);
|
||||
} else {
|
||||
panic!("Expected Store format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op1stdisp8_abcd<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
recipe_op1stdisp8(func, inst, sink)
|
||||
}
|
||||
|
||||
fn recipe_mp1stdisp8<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Store { args, offset, .. } = func.dfg[inst] {
|
||||
put_mp1(func.encodings[inst].bits(), sink);
|
||||
modrm_disp8(func.locations[args[1]].unwrap_reg(),
|
||||
func.locations[args[0]].unwrap_reg(),
|
||||
sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put1(offset as u8);
|
||||
} else {
|
||||
panic!("Expected Store format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op1stdisp32<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Store { args, offset, .. } = func.dfg[inst] {
|
||||
put_op1(func.encodings[inst].bits(), sink);
|
||||
modrm_disp32(func.locations[args[1]].unwrap_reg(),
|
||||
func.locations[args[0]].unwrap_reg(),
|
||||
sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
} else {
|
||||
panic!("Expected Store format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op1stdisp32_abcd<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
recipe_op1stdisp32(func, inst, sink)
|
||||
}
|
||||
|
||||
fn recipe_mp1stdisp32<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Store { args, offset, .. } = func.dfg[inst] {
|
||||
put_mp1(func.encodings[inst].bits(), sink);
|
||||
modrm_disp32(func.locations[args[1]].unwrap_reg(),
|
||||
func.locations[args[0]].unwrap_reg(),
|
||||
sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
} else {
|
||||
panic!("Expected Store format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
// Load recipes
|
||||
|
||||
fn recipe_op1ld<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Load { arg, .. } = func.dfg[inst] {
|
||||
put_op1(func.encodings[inst].bits(), sink);
|
||||
modrm_rm(func.locations[arg].unwrap_reg(),
|
||||
func.locations[func.dfg.first_result(inst)].unwrap_reg(),
|
||||
sink);
|
||||
} else {
|
||||
panic!("Expected Load format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op1lddisp8<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Load { arg, offset, .. } = func.dfg[inst] {
|
||||
put_op1(func.encodings[inst].bits(), sink);
|
||||
modrm_disp8(func.locations[arg].unwrap_reg(),
|
||||
func.locations[func.dfg.first_result(inst)].unwrap_reg(),
|
||||
sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put1(offset as u8);
|
||||
} else {
|
||||
panic!("Expected Load format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op1lddisp32<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Load { arg, offset, .. } = func.dfg[inst] {
|
||||
put_op1(func.encodings[inst].bits(), sink);
|
||||
modrm_disp32(func.locations[arg].unwrap_reg(),
|
||||
func.locations[func.dfg.first_result(inst)].unwrap_reg(),
|
||||
sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
} else {
|
||||
panic!("Expected Load format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op2ld<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Load { arg, .. } = func.dfg[inst] {
|
||||
put_op2(func.encodings[inst].bits(), sink);
|
||||
modrm_rm(func.locations[arg].unwrap_reg(),
|
||||
func.locations[func.dfg.first_result(inst)].unwrap_reg(),
|
||||
sink);
|
||||
} else {
|
||||
panic!("Expected Load format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op2lddisp8<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Load { arg, offset, .. } = func.dfg[inst] {
|
||||
put_op2(func.encodings[inst].bits(), sink);
|
||||
modrm_disp8(func.locations[arg].unwrap_reg(),
|
||||
func.locations[func.dfg.first_result(inst)].unwrap_reg(),
|
||||
sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put1(offset as u8);
|
||||
} else {
|
||||
panic!("Expected Load format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
fn recipe_op2lddisp32<CS: CodeSink + ?Sized>(func: &Function, inst: Inst, sink: &mut CS) {
|
||||
if let InstructionData::Load { arg, offset, .. } = func.dfg[inst] {
|
||||
put_op2(func.encodings[inst].bits(), sink);
|
||||
modrm_disp32(func.locations[arg].unwrap_reg(),
|
||||
func.locations[func.dfg.first_result(inst)].unwrap_reg(),
|
||||
sink);
|
||||
let offset: i32 = offset.into();
|
||||
sink.put4(offset as u32);
|
||||
} else {
|
||||
panic!("Expected Load format: {:?}", func.dfg[inst]);
|
||||
}
|
||||
}
|
||||
|
||||
@@ -11,8 +11,8 @@
|
||||
|
||||
/// Check that `x` is the same as `y`.
|
||||
#[allow(dead_code)]
|
||||
pub fn is_equal<T: Eq + Copy>(x: T, y: T) -> bool {
|
||||
x == y
|
||||
pub fn is_equal<T: Eq + Copy, O: Into<T> + Copy>(x: T, y: O) -> bool {
|
||||
x == y.into()
|
||||
}
|
||||
|
||||
/// Check that `x` can be represented as a `wd`-bit signed integer with `sc` low zero bits.
|
||||
|
||||
Reference in New Issue
Block a user