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Encodings for load/store instructions.

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We don't support the full set of Intel addressing modes yet. So far we
have:

- Register indirect, no displacement.
- Register indirect, 8-bit signed displacement.
- Register indirect, 32-bit signed displacement.

The SIB addressing modes will need new Cretonne instruction formats to
represent.
This commit is contained in:
Jakob Stoklund Olesen
2017-05-12 14:26:44 -07:00
parent f4929825ca
commit bd8230411a
5 changed files with 470 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files

57
lib/cretonne/meta/isa/intel/encodings.py
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@@ -4,15 +4,15 @@ Intel Encodings.
from __future__ import absolute_import
from base import instructions as base
from .defs import I32
from .recipes import Op1rr, Op1rc, Op1rib, Op1rid
from .recipes import OP
from . import recipes as rcp
from .recipes import OP, OP0F, MP66
I32.enc(base.iadd.i32, Op1rr, OP(0x01))
I32.enc(base.isub.i32, Op1rr, OP(0x29))
I32.enc(base.iadd.i32, rcp.Op1rr, OP(0x01))
I32.enc(base.isub.i32, rcp.Op1rr, OP(0x29))
I32.enc(base.band.i32, Op1rr, OP(0x21))
I32.enc(base.bor.i32, Op1rr, OP(0x09))
I32.enc(base.bxor.i32, Op1rr, OP(0x31))
I32.enc(base.band.i32, rcp.Op1rr, OP(0x21))
I32.enc(base.bor.i32, rcp.Op1rr, OP(0x09))
I32.enc(base.bxor.i32, rcp.Op1rr, OP(0x31))
# Immediate instructions with sign-extended 8-bit and 32-bit immediate.
for inst, r in [
@@ -20,12 +20,45 @@ for inst, r in [
(base.band_imm.i32, 4),
(base.bor_imm.i32, 1),
(base.bxor_imm.i32, 6)]:
I32.enc(inst, Op1rib, OP(0x83, rrr=r))
I32.enc(inst, Op1rid, OP(0x81, rrr=r))
I32.enc(inst, rcp.Op1rib, OP(0x83, rrr=r))
I32.enc(inst, rcp.Op1rid, OP(0x81, rrr=r))
# 32-bit shifts and rotates.
# Note that the dynamic shift amount is only masked by 5 or 6 bits; the 8-bit
# and 16-bit shifts would need explicit masking.
I32.enc(base.ishl.i32.i32, Op1rc, OP(0xd3, rrr=4))
I32.enc(base.ushr.i32.i32, Op1rc, OP(0xd3, rrr=5))
I32.enc(base.sshr.i32.i32, Op1rc, OP(0xd3, rrr=7))
I32.enc(base.ishl.i32.i32, rcp.Op1rc, OP(0xd3, rrr=4))
I32.enc(base.ushr.i32.i32, rcp.Op1rc, OP(0xd3, rrr=5))
I32.enc(base.sshr.i32.i32, rcp.Op1rc, OP(0xd3, rrr=7))
# Loads and stores.
I32.enc(base.store.i32.i32, rcp.Op1st, OP(0x89))
I32.enc(base.store.i32.i32, rcp.Op1stDisp8, OP(0x89))
I32.enc(base.store.i32.i32, rcp.Op1stDisp32, OP(0x89))
I32.enc(base.istore16.i32.i32, rcp.Mp1st, MP66(0x89))
I32.enc(base.istore16.i32.i32, rcp.Mp1stDisp8, MP66(0x89))
I32.enc(base.istore16.i32.i32, rcp.Mp1stDisp32, MP66(0x89))
I32.enc(base.istore8.i32.i32, rcp.Op1st_abcd, OP(0x88))
I32.enc(base.istore8.i32.i32, rcp.Op1stDisp8_abcd, OP(0x88))
I32.enc(base.istore8.i32.i32, rcp.Op1stDisp32_abcd, OP(0x88))
I32.enc(base.load.i32.i32, rcp.Op1ld, OP(0x8b))
I32.enc(base.load.i32.i32, rcp.Op1ldDisp8, OP(0x8b))
I32.enc(base.load.i32.i32, rcp.Op1ldDisp32, OP(0x8b))
I32.enc(base.uload16.i32.i32, rcp.Op2ld, OP0F(0xb7))
I32.enc(base.uload16.i32.i32, rcp.Op2ldDisp8, OP0F(0xb7))
I32.enc(base.uload16.i32.i32, rcp.Op2ldDisp32, OP0F(0xb7))
I32.enc(base.sload16.i32.i32, rcp.Op2ld, OP0F(0xbf))
I32.enc(base.sload16.i32.i32, rcp.Op2ldDisp8, OP0F(0xbf))
I32.enc(base.sload16.i32.i32, rcp.Op2ldDisp32, OP0F(0xbf))
I32.enc(base.uload8.i32.i32, rcp.Op2ld, OP0F(0xb6))
I32.enc(base.uload8.i32.i32, rcp.Op2ldDisp8, OP0F(0xb6))
I32.enc(base.uload8.i32.i32, rcp.Op2ldDisp32, OP0F(0xb6))
I32.enc(base.sload8.i32.i32, rcp.Op2ld, OP0F(0xbe))
I32.enc(base.sload8.i32.i32, rcp.Op2ldDisp8, OP0F(0xbe))
I32.enc(base.sload8.i32.i32, rcp.Op2ldDisp32, OP0F(0xbe))