cranelift: remove load_complex and store_complex (#3976)

This change removes all variants of `load*_complex` and `store*_complex`
from Cranelift; this is a breaking change to the instructions exposed by
CLIF. The complete list of instructions removed is: `load_complex`,
`store_complex`, `uload8_complex`, `sload8_complex`, `istore8_complex`,
`sload8_complex`, `uload16_complex`, `sload16_complex`,
`istore16_complex`, `uload32_complex`, `sload32_complex`,
`istore32_complex`, `uload8x8_complex`, `sload8x8_complex`,
`sload16x4_complex`, `uload16x4_complex`, `uload32x2_complex`,
`sload32x2_complex`.

The rationale for this removal is that the Cranelift backend now has the
ability to pattern-match multiple upstream additions in order to
calculate the address to access. Previously, this was not possible so
the `*_complex` instructions were needed. Over time, these instructions
have fallen out of use in this repository, making the additional
overhead of maintaining them a chore.

cranelift/filetests/filetests/isa/aarch64/amodes.clif

@@ -2,70 +2,6 @@ test compile precise-output
 set unwind_info=false
 target aarch64
 
-function %f0(i64, i32) -> i32 {
-block0(v0: i64, v1: i32):
-  v2 = uextend.i64 v1
-  v3 = load_complex.i32 v0+v2
-  return v3
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 2)
-;   Inst 0:   ldr w0, [x0, w1, UXTW]
-;   Inst 1:   ret
-; }}
-
-function %f2(i64, i32) -> i32 {
-block0(v0: i64, v1: i32):
-  v2 = uextend.i64 v1
-  v3 = load_complex.i32 v2+v0
-  return v3
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 2)
-;   Inst 0:   ldr w0, [x0, w1, UXTW]
-;   Inst 1:   ret
-; }}
-
-function %f3(i64, i32) -> i32 {
-block0(v0: i64, v1: i32):
-  v2 = sextend.i64 v1
-  v3 = load_complex.i32 v0+v2
-  return v3
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 2)
-;   Inst 0:   ldr w0, [x0, w1, SXTW]
-;   Inst 1:   ret
-; }}
-
-function %f4(i64, i32) -> i32 {
-block0(v0: i64, v1: i32):
-  v2 = sextend.i64 v1
-  v3 = load_complex.i32 v2+v0
-  return v3
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 2)
-;   Inst 0:   ldr w0, [x0, w1, SXTW]
-;   Inst 1:   ret
-; }}
-
 function %f5(i64, i32) -> i32 {
 block0(v0: i64, v1: i32):
   v2 = sextend.i64 v1
@@ -294,91 +230,6 @@ block0(v0: i32, v1: i32):
 ;   Inst 2:   ret
 ; }}
 
-function %f16(i64) -> i32 {
-block0(v0: i64):
-  v1 = iconst.i32 0
-  v2 = uextend.i64 v1
-  v3 = load_complex.i32 v0+v2
-  return v3
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 2)
-;   Inst 0:   ldr w0, [x0]
-;   Inst 1:   ret
-; }}
-
-function %f17(i64) -> i32 {
-block0(v0: i64):
-  v1 = iconst.i32 4
-  v2 = uextend.i64 v1
-  v3 = load_complex.i32 v0+v2
-  return v3
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 2)
-;   Inst 0:   ldur w0, [x0, #4]
-;   Inst 1:   ret
-; }}
-
-function %f18(i64, i32) -> i16x8 {
-block0(v0: i64, v1: i32):
-  v2 = uextend.i64 v1
-  v3 = sload8x8_complex v2+v0
-  return v3
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 3)
-;   Inst 0:   ldr d0, [x0, w1, UXTW]
-;   Inst 1:   sxtl v0.8h, v0.8b
-;   Inst 2:   ret
-; }}
-
-function %f19(i64, i64) -> i32x4 {
-block0(v0: i64, v1: i64):
-  v2 = uload16x4_complex v0+v1+8
-  return v2
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 4)
-;   Inst 0:   add x0, x0, x1
-;   Inst 1:   ldr d0, [x0, #8]
-;   Inst 2:   uxtl v0.4s, v0.4h
-;   Inst 3:   ret
-; }}
-
-function %f20(i64, i32) -> i64x2 {
-block0(v0: i64, v1: i32):
-  v2 = sextend.i64 v1
-  v3 = uload32x2_complex v2+v0
-  return v3
-}
-
-; VCode_ShowWithRRU {{
-;   Entry block: 0
-; Block 0:
-;   (original IR block: block0)
-;   (instruction range: 0 .. 3)
-;   Inst 0:   ldr d0, [x0, w1, SXTW]
-;   Inst 1:   uxtl v0.2d, v0.2s
-;   Inst 2:   ret
-; }}
-
 function %f18(i64, i64, i64) -> i32 {
 block0(v0: i64, v1: i64, v2: i64):
   v3 = iconst.i32 -4098

cranelift/filetests/filetests/parser/tiny.clif

@@ -152,13 +152,9 @@ block0(v1: i32):
     v6 = load.i64 aligned notrap v1
     v7 = load.i64 v1-12
     v8 = load.i64 notrap v1+0x1_0000
-    v9 = load_complex.i64 v1+v2
-    v10 = load_complex.i64 v1+v2+0x1
     store v2, v1
     store aligned v3, v1+12
     store notrap aligned v3, v1-12
-    store_complex v3, v1+v2
-    store_complex v3, v1+v2+0x1
 }
 ; sameln: function %memory(i32) fast {
 ; nextln: block0(v1: i32):
@@ -169,13 +165,9 @@ block0(v1: i32):
 ; nextln:     v6 = load.i64 notrap aligned v1
 ; nextln:     v7 = load.i64 v1-12
 ; nextln:     v8 = load.i64 notrap v1+0x0001_0000
-; nextln:     v9 = load_complex.i64 v1+v2
-; nextln:     v10 = load_complex.i64 v1+v2+1
 ; nextln:     store v2, v1
 ; nextln:     store aligned v3, v1+12
 ; nextln:     store notrap aligned v3, v1-12
-; nextln:     store_complex v3, v1+v2
-; nextln:     store_complex v3, v1+v2+1
 
 function %cond_traps(i32) {
 block0(v0: i32):