Add an instruction shrinking pass.

When an instruction has multiple valid encodings, such as with and
without a REX prefix on x86-64, Cretonne typically picks the encoding
which gives the register allocator the most flexibility, which is
typically the longest encoding. This patch adds a pass that runs after
register allocation that picks the smallest encoding, working within the
constraints of the register allocator's choices. The result is smaller
and easier to read encodings.

In the future, we may want to merge this pass into the relaxation pass,
or possibly fold it into the final encoding step, however for now, a
discrete pass will suffice.

cranelift/filetests/isa/x86/prologue-epilogue.cton

@@ -228,4 +228,4 @@ ebb4:
 
 ; check: function %divert
 ; check: regmove v5, %rcx -> %rbx
-; check: [RexOp1popq#58,%rbx]                v15 = x86_pop.i64
+; check: [Op1popq#58,%rbx]                   v15 = x86_pop.i64

cranelift/filetests/isa/x86/shrink.cton

@@ -0,0 +1,29 @@
+test binemit
+set is_64bit=1
+set opt_level=best
+isa x86
+
+; Test that instruction shrinking eliminates REX prefixes when possible.
+
+; The binary encodings can be verified with the command:
+;
+;   sed -ne 's/^ *; asm: *//p' filetests/isa/x86/shrink.cton | llvm-mc -show-encoding -triple=x86_64
+;
+
+function %test_shrinking(i32) -> i32 {
+ebb0(v0: i32 [ %rdi ]):
+           ; asm: movl $0x2,%eax
+[-,%rcx]   v1 = iconst.i32 2     ; bin: b9 00000002
+           ; asm: subl %ecx,%edi
+[-,%rdi]   v2 = isub v0, v1      ; bin: 29 cf
+           return v2
+}
+
+function %test_not_shrinking(i32) -> i32 {
+ebb0(v0: i32 [ %r8 ]):
+           ; asm: movl $0x2,%eax
+[-,%rcx]   v1 = iconst.i32 2     ; bin: b9 00000002
+           ; asm: subl %ecx,%edi
+[-,%r8]    v2 = isub v0, v1      ; bin: 41 29 c8
+           return v2
+}