T0b1/wasmtime
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

ISLE: use lower_to_amode inside sink_load implementation

Browse Source
This commit is contained in:
Nick Fitzgerald
2021-11-10 13:21:48 -08:00
parent 7a568b19b4
commit bbb4949128
1 changed files with 4 additions and 18 deletions
Download Patch File Download Diff File Expand all files Collapse all files

22
cranelift/codegen/src/isa/x64/lower/isle.rs
View File

@@ -8,13 +8,12 @@ use super::{
is_mergeable_load, lower_to_amode, AluRmiROpcode, Inst as MInst, OperandSize, Reg, RegMemImm,
Writable,
};
use crate::isa::x64::inst::args::SyntheticAmode;
use crate::isa::x64::settings as x64_settings;
use crate::{
ir::{immediates::*, types::*, Inst, InstructionData, Opcode, Value, ValueList},
isa::x64::inst::{
args::{
Amode, Avx512Opcode, CmpOpcode, ExtMode, Imm8Reg, RegMem, ShiftKind, SseOpcode, CC,
},
args::{Avx512Opcode, CmpOpcode, ExtMode, Imm8Reg, RegMem, ShiftKind, SseOpcode, CC},
x64_map_regs, RegMapper,
},
machinst::{get_output_reg, InsnInput, InsnOutput, LowerCtx},
@@ -369,22 +368,9 @@ where
fn sink_load(&mut self, load: &SinkableLoad) -> RegMemImm {
self.lower_ctx.sink_inst(load.inst);
let flags = self
.lower_ctx
.memflags(load.inst)
.expect("sinkable loads should have memflags");
let base = self
.lower_ctx
.put_input_in_regs(load.addr_input.insn, load.addr_input.input)
.only_reg()
.unwrap();
let addr = lower_to_amode(self.lower_ctx, load.addr_input, load.offset);
RegMemImm::Mem {
addr: Amode::imm_reg(load.offset as u32, base)
.with_flags(flags)
.into(),
addr: SyntheticAmode::Real(addr),
}
}