Rustfmt

cranelift/codegen/src/regalloc/coalescing.rs

@@ -17,12 +17,12 @@ use crate::regalloc::affinity::Affinity;
 use crate::regalloc::liveness::Liveness;
 use crate::regalloc::virtregs::{VirtReg, VirtRegs};
 use crate::timing;
+use alloc::vec::Vec;
 use core::cmp;
 use core::fmt;
 use core::iter;
 use core::slice;
 use log::debug;
-use alloc::vec::Vec;
 
 // # Implementation
 //

cranelift/codegen/src/regalloc/liveness.rs

@@ -183,9 +183,9 @@ use crate::isa::{EncInfo, OperandConstraint, TargetIsa};
 use crate::regalloc::affinity::Affinity;
 use crate::regalloc::liverange::LiveRange;
 use crate::timing;
+use alloc::vec::Vec;
 use core::mem;
 use core::ops::Index;
-use alloc::vec::Vec;
 
 /// A set of live ranges, indexed by value number.
 type LiveRangeSet = SparseMap<Value, LiveRange>;

cranelift/codegen/src/regalloc/liverange.rs

@@ -476,8 +476,8 @@ mod tests {
     use crate::entity::EntityRef;
     use crate::ir::{Ebb, Inst, Value};
     use crate::ir::{ExpandedProgramPoint, ProgramOrder};
-    use core::cmp::Ordering;
     use alloc::vec::Vec;
+    use core::cmp::Ordering;
 
     // Dummy program order which simply compares indexes.
     // It is assumed that EBBs have indexes that are multiples of 10, and instructions have indexes

cranelift/codegen/src/regalloc/pressure.rs

@@ -275,9 +275,9 @@ mod tests {
     use super::Pressure;
     use crate::isa::{RegClass, TargetIsa};
     use crate::regalloc::RegisterSet;
+    use alloc::boxed::Box;
     use core::borrow::Borrow;
     use core::str::FromStr;
-    use alloc::boxed::Box;
     use target_lexicon::triple;
 
     // Make an arm32 `TargetIsa`, if possible.

cranelift/codegen/src/regalloc/reload.rs

@@ -21,8 +21,8 @@ use crate::regalloc::live_value_tracker::{LiveValue, LiveValueTracker};
 use crate::regalloc::liveness::Liveness;
 use crate::timing;
 use crate::topo_order::TopoOrder;
-use log::debug;
 use alloc::vec::Vec;
+use log::debug;
 
 /// Reusable data structures for the reload pass.
 pub struct Reload {

cranelift/codegen/src/regalloc/solver.rs

@@ -104,12 +104,12 @@ use crate::entity::{SparseMap, SparseMapValue};
 use crate::ir::Value;
 use crate::isa::{RegClass, RegUnit};
 use crate::regalloc::register_set::RegSetIter;
+use alloc::vec::Vec;
 use core::cmp;
 use core::fmt;
 use core::mem;
 use core::u16;
 use log::debug;
-use alloc::vec::Vec;
 
 /// A variable in the constraint problem.
 ///
@@ -1159,8 +1159,8 @@ mod tests {
     use crate::ir::Value;
     use crate::isa::{RegClass, RegInfo, RegUnit, TargetIsa};
     use crate::regalloc::RegisterSet;
-    use core::str::FromStr;
     use alloc::boxed::Box;
+    use core::str::FromStr;
     use target_lexicon::triple;
 
     // Make an arm32 `TargetIsa`, if possible.

cranelift/codegen/src/regalloc/spilling.rs

@@ -27,9 +27,9 @@ use crate::regalloc::pressure::Pressure;
 use crate::regalloc::virtregs::VirtRegs;
 use crate::timing;
 use crate::topo_order::TopoOrder;
+use alloc::vec::Vec;
 use core::fmt;
 use log::debug;
-use alloc::vec::Vec;
 
 /// Return a top-level register class which contains `unit`.
 fn toprc_containing_regunit(unit: RegUnit, reginfo: &RegInfo) -> RegClass {

cranelift/codegen/src/regalloc/virtregs.rs

@@ -18,11 +18,11 @@ use crate::entity::{EntityList, ListPool};
 use crate::entity::{Keys, PrimaryMap, SecondaryMap};
 use crate::ir::{Function, Value};
 use crate::packed_option::PackedOption;
+use alloc::vec::Vec;
 use core::cmp::Ordering;
 use core::fmt;
 use core::slice;
 use smallvec::SmallVec;
-use alloc::vec::Vec;
 
 /// A virtual register reference.
 #[derive(Copy, Clone, PartialEq, Eq, Hash, PartialOrd, Ord)]