Add a TargetIsa::allocatable_registers() method.

This gives the target ISA a chance to reserve registers like the stack
pointer or hard-wired 0 registers like %x0 on RISC-V.

lib/cretonne/src/regalloc/coloring.rs

@@ -101,8 +101,7 @@ impl Coloring {
             encinfo: isa.encoding_info(),
             domtree: domtree,
             liveness: liveness,
-            // TODO: Ask the target ISA about reserved registers etc.
-            usable_regs: AllocatableSet::new(),
+            usable_regs: isa.allocatable_registers(func),
         };
         ctx.run(self, func, tracker)
     }

lib/cretonne/src/regalloc/mod.rs

@@ -11,4 +11,5 @@ pub mod coloring;
 mod affinity;
 mod context;
 
+pub use self::allocatable_set::AllocatableSet;
 pub use self::context::Context;