diff --git a/cranelift/Cargo.toml b/cranelift/Cargo.toml index 209ff9e22e..4e6d885ab7 100644 --- a/cranelift/Cargo.toml +++ b/cranelift/Cargo.toml @@ -51,4 +51,5 @@ disas = ["capstone"] enable-peepmatic = ["cranelift-codegen/enable-peepmatic", "cranelift-filetests/enable-peepmatic"] wasm = ["wat", "cranelift-wasm"] experimental_x64 = ["cranelift-codegen/x64"] +experimental_arm32 = ["cranelift-codegen/arm32"] souper-harvest = ["cranelift-codegen/souper-harvest", "rayon"] diff --git a/cranelift/codegen/Cargo.toml b/cranelift/codegen/Cargo.toml index 351e0dce12..3a1315dca2 100644 --- a/cranelift/codegen/Cargo.toml +++ b/cranelift/codegen/Cargo.toml @@ -61,15 +61,14 @@ unwind = ["gimli"] # ISA targets for which we should build. # If no ISA targets are explicitly enabled, the ISA target for the host machine is enabled. x86 = [] -arm32 = [] arm64 = [] riscv = [] x64 = [] # New work-in-progress codegen backend for x86_64 based on the new isel. +arm32 = [] # Work-in-progress codegen backend for ARM. # Option to enable all architectures. all-arch = [ "x86", - "arm32", "arm64", "riscv" ] diff --git a/cranelift/filetests/filetests/vcode/arm32/aluops.clif b/cranelift/filetests/filetests/vcode/arm32/aluops.clif index 3dcd47cdba..fe47fd37f1 100644 --- a/cranelift/filetests/filetests/vcode/arm32/aluops.clif +++ b/cranelift/filetests/filetests/vcode/arm32/aluops.clif @@ -1,5 +1,6 @@ test compile target arm +feature "experimental_arm32" function %iadd(i8, i8) -> i8 { block0(v0: i8, v1: i8): diff --git a/cranelift/filetests/filetests/vcode/arm32/bitops.clif b/cranelift/filetests/filetests/vcode/arm32/bitops.clif index 9ec808c290..77031faa68 100644 --- a/cranelift/filetests/filetests/vcode/arm32/bitops.clif +++ b/cranelift/filetests/filetests/vcode/arm32/bitops.clif @@ -1,5 +1,6 @@ test compile target arm +feature "experimental_arm32" function %bitrev_i8(i8) -> i8 { block0(v0: i8): diff --git a/cranelift/filetests/filetests/vcode/arm32/cond.clif b/cranelift/filetests/filetests/vcode/arm32/cond.clif index 2121c8903f..4924c4e80d 100644 --- a/cranelift/filetests/filetests/vcode/arm32/cond.clif +++ b/cranelift/filetests/filetests/vcode/arm32/cond.clif @@ -1,5 +1,6 @@ test compile target arm +feature "experimental_arm32" function %icmp(i32, i32) -> b1 { block0(v0: i32, v1: i32): diff --git a/cranelift/filetests/filetests/vcode/arm32/constants.clif b/cranelift/filetests/filetests/vcode/arm32/constants.clif index 19a416bcee..5da12b8782 100644 --- a/cranelift/filetests/filetests/vcode/arm32/constants.clif +++ b/cranelift/filetests/filetests/vcode/arm32/constants.clif @@ -1,5 +1,6 @@ test compile target arm +feature "experimental_arm32" function %b1() -> b1 { block0: diff --git a/cranelift/filetests/filetests/vcode/arm32/control-flow.clif b/cranelift/filetests/filetests/vcode/arm32/control-flow.clif index 0822806501..0148d69243 100644 --- a/cranelift/filetests/filetests/vcode/arm32/control-flow.clif +++ b/cranelift/filetests/filetests/vcode/arm32/control-flow.clif @@ -1,5 +1,6 @@ test compile target arm +feature "experimental_arm32" function %brnz(b1) -> i32 { block0(v0: b1): diff --git a/cranelift/filetests/filetests/vcode/arm32/extend.clif b/cranelift/filetests/filetests/vcode/arm32/extend.clif index 0939ecdf2b..3cc1733a0a 100644 --- a/cranelift/filetests/filetests/vcode/arm32/extend.clif +++ b/cranelift/filetests/filetests/vcode/arm32/extend.clif @@ -1,5 +1,6 @@ test compile target arm +feature "experimental_arm32" function %uextend_i8_i32(i8) -> i32 { block0(v0: i8): diff --git a/cranelift/filetests/filetests/vcode/arm32/params.clif b/cranelift/filetests/filetests/vcode/arm32/params.clif index 6215a78022..1e4ee30911 100644 --- a/cranelift/filetests/filetests/vcode/arm32/params.clif +++ b/cranelift/filetests/filetests/vcode/arm32/params.clif @@ -1,5 +1,6 @@ test compile target arm +feature "experimental_arm32" function %args(i32) -> i32 { sig0 = (i32, i32, i32, i32) -> i32 diff --git a/cranelift/filetests/filetests/vcode/arm32/shift-rotate.clif b/cranelift/filetests/filetests/vcode/arm32/shift-rotate.clif index 1acd7a30e0..67e4a11e57 100644 --- a/cranelift/filetests/filetests/vcode/arm32/shift-rotate.clif +++ b/cranelift/filetests/filetests/vcode/arm32/shift-rotate.clif @@ -1,5 +1,6 @@ test compile target arm +feature "experimental_arm32" function %ishl_i8(i8, i8) -> i8 { block0(v0: i8, v1: i8): diff --git a/cranelift/filetests/src/runone.rs b/cranelift/filetests/src/runone.rs index 14bbb539ce..310b173cf0 100644 --- a/cranelift/filetests/src/runone.rs +++ b/cranelift/filetests/src/runone.rs @@ -9,7 +9,7 @@ use cranelift_codegen::print_errors::pretty_verifier_error; use cranelift_codegen::settings::Flags; use cranelift_codegen::timing; use cranelift_codegen::verify_function; -use cranelift_reader::{parse_test, IsaSpec, ParseOptions}; +use cranelift_reader::{parse_test, Feature, IsaSpec, ParseOptions}; use log::info; use std::borrow::Cow; use std::fs; @@ -51,6 +51,15 @@ pub fn run( } }; + #[cfg(not(feature = "experimental_arm32"))] + if testfile + .features + .contains(&Feature::With("experimental_arm32")) + { + println!("skipped {:?}: no experimental_arm32 feature", path); + return Ok(started.elapsed()); + } + if testfile.functions.is_empty() { anyhow::bail!("no functions found"); } diff --git a/cranelift/frontend/src/frontend.rs b/cranelift/frontend/src/frontend.rs index 802a13ff6a..3b9263301a 100644 --- a/cranelift/frontend/src/frontend.rs +++ b/cranelift/frontend/src/frontend.rs @@ -972,12 +972,13 @@ mod tests { let shared_builder = settings::builder(); let shared_flags = settings::Flags::new(shared_builder); - let triple = ::target_lexicon::Triple::from_str("arm").expect("Couldn't create arm triple"); + let triple = + ::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple"); let target = isa::lookup(triple) .ok() .map(|b| b.finish(shared_flags)) - .expect("This test requires arm support."); + .expect("This test requires riscv32 support."); let mut sig = Signature::new(target.default_call_conv()); sig.returns.push(AbiParam::new(I32)); @@ -1033,12 +1034,13 @@ block0: let shared_builder = settings::builder(); let shared_flags = settings::Flags::new(shared_builder); - let triple = ::target_lexicon::Triple::from_str("arm").expect("Couldn't create arm triple"); + let triple = + ::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple"); let target = isa::lookup(triple) .ok() .map(|b| b.finish(shared_flags)) - .expect("This test requires arm support."); + .expect("This test requires riscv32 support."); let mut sig = Signature::new(target.default_call_conv()); sig.returns.push(AbiParam::new(I32)); @@ -1090,12 +1092,13 @@ block0: let shared_builder = settings::builder(); let shared_flags = settings::Flags::new(shared_builder); - let triple = ::target_lexicon::Triple::from_str("arm").expect("Couldn't create arm triple"); + let triple = + ::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple"); let target = isa::lookup(triple) .ok() .map(|b| b.finish(shared_flags)) - .expect("This test requires arm support."); + .expect("This test requires riscv32 support."); let mut sig = Signature::new(target.default_call_conv()); sig.returns.push(AbiParam::new(I32)); @@ -1150,12 +1153,13 @@ block0: let shared_builder = settings::builder(); let shared_flags = settings::Flags::new(shared_builder); - let triple = ::target_lexicon::Triple::from_str("arm").expect("Couldn't create arm triple"); + let triple = + ::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple"); let target = isa::lookup(triple) .ok() .map(|b| b.finish(shared_flags)) - .expect("This test requires arm support."); + .expect("This test requires riscv32 support."); let mut sig = Signature::new(target.default_call_conv()); sig.returns.push(AbiParam::new(I32)); @@ -1202,12 +1206,13 @@ block0: let shared_builder = settings::builder(); let shared_flags = settings::Flags::new(shared_builder); - let triple = ::target_lexicon::Triple::from_str("arm").expect("Couldn't create arm triple"); + let triple = + ::target_lexicon::Triple::from_str("riscv32").expect("Couldn't create riscv32 triple"); let target = isa::lookup(triple) .ok() .map(|b| b.finish(shared_flags)) - .expect("This test requires arm support."); + .expect("This test requires riscv32 support."); let mut sig = Signature::new(target.default_call_conv()); sig.returns.push(AbiParam::new(I32));