From ba7b874ca3664d0b4916cf8f41e03813d5e2798b Mon Sep 17 00:00:00 2001
From: Afonso Bordado <afonso360@users.noreply.github.com>
Date: Tue, 25 Oct 2022 18:03:04 +0100
Subject: [PATCH] cranelift: Add RISC-V disassembly capabilities to clif-util
 (#5117)

This just correctly maps our RISC-V ISA to capstone.
---
 cranelift/src/disasm.rs | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/cranelift/src/disasm.rs b/cranelift/src/disasm.rs
index a950d6b98f..67caf28bc3 100644
--- a/cranelift/src/disasm.rs
+++ b/cranelift/src/disasm.rs
@@ -118,6 +118,18 @@ cfg_if! {
                     .mode(arch::sysz::ArchMode::Default)
                     .build()
                     .map_err(map_caperr)?,
+                Architecture::Riscv64 {..} => {
+                    let mut cs = Capstone::new()
+                        .riscv()
+                        .mode(arch::riscv::ArchMode::RiscV64)
+                        .build()
+                        .map_err(map_caperr)?;
+                    // Similar to AArch64, RISC-V uses inline constants rather than a separate
+                    // constant pool. We want to skip dissasembly over inline constants instead
+                    // of stopping on invalid bytes.
+                    cs.set_skipdata(true).map_err(map_caperr)?;
+                    cs
+                }
                 _ => anyhow::bail!("Unknown ISA"),
             };