Add a t8jccd_long encoding recipe for brz.b1 and brnz.b1 in 32-bit mode.

The register allocator can't handle branches with constrained register
operands, and the brz.b1/brnz.b1 instructions only have the t8jccd_abcd
in 32-bit mode where no REX prefixes are possible.

This adds a worst case encoding for those cases where a b1 value lives
in a non-ABCD register.

cranelift/filetests/isa/intel/binary32.cton

@@ -1,5 +1,6 @@
 ; binary emission of 32-bit code.
 test binemit
+set is_compressed
 isa intel haswell
 
 ; The binary encodings can be verified with the command:
@@ -393,3 +394,30 @@ ebb1:
 ebb2:
     trap user0                                  ; bin: 0f 0b
 }
+
+; Special branch encodings only for I32 mode.
+function %special_branches() {
+ebb0:
+    [-,%rcx]            v1 = iconst.i32 1
+    [-,%rsi]            v2 = iconst.i32 2
+    [-,%rdi]            v3 = icmp eq v1, v2
+    [-,%rbx]            v4 = icmp ugt v1, v2
+
+    ; asm: testl $0xff, %edi
+    ; asm: je ebb1
+    brz v3, ebb1                                ; bin: f7 c7 000000ff 0f 84 00000015
+    ; asm: testb %bl, %bl
+    ; asm: je ebb1
+    brz v4, ebb1                                ; bin: 84 db 74 11
+    ; asm: testl $0xff, %edi
+    ; asm: jne ebb1
+    brnz v3, ebb1                               ; bin: f7 c7 000000ff 0f 85 00000005
+    ; asm: testb %bl, %bl
+    ; asm: jne ebb1
+    brnz v4, ebb1                               ; bin: 84 db 75 01
+
+    return
+
+ebb1:
+    return
+}