Add x86 legalization for SIMD ineg

cranelift/codegen/src/isa/x86/enc_tables.rs

@@ -5,6 +5,7 @@ use crate::bitset::BitSet;
 use crate::cursor::{Cursor, FuncCursor};
 use crate::flowgraph::ControlFlowGraph;
 use crate::ir::condcodes::{FloatCC, IntCC};
+use crate::ir::immediates::V128Imm;
 use crate::ir::types::*;
 use crate::ir::{self, Function, Inst, InstBuilder};
 use crate::isa::constraints::*;
@@ -1090,3 +1091,27 @@ fn convert_insertlane(
         }
     }
 }
+
+/// For SIMD negation, convert an `ineg` to a `vconst + isub`.
+fn convert_ineg(
+    inst: ir::Inst,
+    func: &mut ir::Function,
+    _cfg: &mut ControlFlowGraph,
+    _isa: &dyn TargetIsa,
+) {
+    let mut pos = FuncCursor::new(func).at_inst(inst);
+    pos.use_srcloc(inst);
+
+    if let ir::InstructionData::Unary {
+        opcode: ir::Opcode::Ineg,
+        arg,
+    } = pos.func.dfg[inst]
+    {
+        let value_type = pos.func.dfg.value_type(arg);
+        if value_type.is_vector() && value_type.lane_type().is_int() {
+            let zero_immediate = pos.func.dfg.constants.insert(V128Imm::from(0).to_vec());
+            let zero_value = pos.ins().vconst(value_type, zero_immediate); // this should be legalized to a PXOR
+            pos.func.dfg.replace(inst).isub(zero_value, arg);
+        }
+    }
+}