Add a verifier pass for CPU flags.

Only one CPU flags value can be live at a time, and some instructions
clobber the flags.

lib/cretonne/src/ir/dfg.rs

@@ -4,7 +4,7 @@ use entity::{PrimaryMap, EntityMap};
 use isa::TargetIsa;
 use ir::builder::{InsertBuilder, ReplaceBuilder};
 use ir::extfunc::ExtFuncData;
-use ir::instructions::{InstructionData, CallInfo};
+use ir::instructions::{InstructionData, CallInfo, BranchInfo};
 use ir::layout::{Cursor, LayoutCursorInserter};
 use ir::types;
 use ir::{Ebb, Inst, Value, Type, SigRef, Signature, FuncRef, ValueList, ValueListPool};
@@ -613,6 +613,11 @@ impl DataFlowGraph {
         }
     }
 
+    /// Check if `inst` is a branch.
+    pub fn analyze_branch(&self, inst: Inst) -> BranchInfo {
+        self.insts[inst].analyze_branch(&self.value_lists)
+    }
+
     /// Compute the type of an instruction result from opcode constraints and call signatures.
     ///
     /// This computes the same sequence of result types that `make_inst_results()` above would

lib/cretonne/src/ir/types.rs

@@ -200,6 +200,14 @@ impl Type {
         }
     }
 
+    /// Is this a CPU flags type?
+    pub fn is_flags(self) -> bool {
+        match self {
+            IFLAGS | FFLAGS => true,
+            _ => false,
+        }
+    }
+
     /// Get log_2 of the number of lanes in this SIMD vector type.
     ///
     /// All SIMD types have a lane count that is a power of two and no larger than 256, so this