Add SIMD bitselect instruction and x86 legalization

This new instructions matches the `bitselect` behavior described in the WASM SIMD spec (https://github.com/WebAssembly/simd/blob/master/proposals/simd/SIMD.md#bitwise-select)
This commit is contained in:
Andrew Brown
2019-10-11 15:12:46 -07:00
parent 8f74333662
commit b927c55511
4 changed files with 65 additions and 0 deletions

View File

@@ -20,7 +20,9 @@ pub(crate) fn define(shared: &mut SharedDefinitions, x86_instructions: &Instruct
// List of instructions.
let insts = &shared.instructions;
let band = insts.by_name("band");
let band_not = insts.by_name("band_not");
let bitcast = insts.by_name("bitcast");
let bitselect = insts.by_name("bitselect");
let bor = insts.by_name("bor");
let bnot = insts.by_name("bnot");
let bxor = insts.by_name("bxor");
@@ -431,6 +433,19 @@ pub(crate) fn define(shared: &mut SharedDefinitions, x86_instructions: &Instruct
);
}
// SIMD select
for ty in ValueType::all_lane_types().filter(allowed_simd_type) {
let bitselect = bitselect.bind(vector(ty, sse_vector_size)); // must bind both x/y and c
narrow.legalize(
def!(d = bitselect(c, x, y)),
vec![
def!(a = band(x, c)),
def!(b = band_not(y, c)),
def!(d = bor(a, b)),
],
);
}
narrow.custom_legalize(shuffle, "convert_shuffle");
narrow.custom_legalize(extractlane, "convert_extractlane");
narrow.custom_legalize(insertlane, "convert_insertlane");

View File

@@ -1199,6 +1199,22 @@ pub(crate) fn define(
.operands_out(vec![a]),
);
let c = &operand_doc("c", Any, "Controlling value to test");
ig.push(
Inst::new(
"bitselect",
r#"
Conditional select of bits.
For each bit in `c`, this instruction selects the corresponding bit from `x` if the bit
in `c` is 1 and the corresponding bit from `y` if the bit in `c` is 0. See also:
`select`, `vselect`.
"#,
)
.operands_in(vec![c, x, y])
.operands_out(vec![a]),
);
let x = &operand("x", Any);
ig.push(