cranelift: Use x64_ prefix to disambiguate with clif in ISLE
Instead of using `m_` like we used to, which was short for "mach inst" but not obvious or clear at all.
This commit is contained in:
Nick Fitzgerald
@@ -73,8 +73,7 @@
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(src Reg)
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(dst WritableReg))
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(LoadEffectiveAddress (addr SyntheticAmode)
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(dst WritableReg))
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))
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(dst WritableReg))))
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(type OperandSize extern
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(enum Size8
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@@ -534,9 +533,9 @@
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(let ((wr WritableReg (temp_writable_reg ty))
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(r Reg (writable_reg_to_reg wr))
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(_ Unit (emit (MInst.XmmRmR (sse_cmp_op $I32X4)
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r
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(RegMem.Reg r)
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wr))))
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r
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(RegMem.Reg r)
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wr))))
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r))
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;; Helper for creating an SSE register holding an `i64x2` from two `i64` values.
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@@ -697,8 +696,8 @@
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;;
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;; Use `m_` prefix (short for "mach inst") to disambiguate with the ISLE-builtin
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;; `and` operator.
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(decl m_and (Type Reg RegMemImm) Reg)
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(rule (m_and ty src1 src2)
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(decl x64_and (Type Reg RegMemImm) Reg)
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(rule (x64_and ty src1 src2)
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(alu_rmi_r ty
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(AluRmiROpcode.And)
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src1
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@@ -766,9 +765,9 @@
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(let ((wr WritableReg (temp_writable_reg ty))
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(r Reg (writable_reg_to_reg wr))
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(_ Unit (emit (MInst.XmmRmR (sse_xor_op ty)
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r
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(RegMem.Reg r)
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wr))))
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r
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(RegMem.Reg r)
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wr))))
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r))
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;; Special case for `f32` zero immediates to use `xorps`.
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@@ -807,14 +806,14 @@
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;; Helper for creating `rotl` instructions (prefixed with "m_", short for "mach
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;; inst", to disambiguate this from clif's `rotl`).
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(decl m_rotl (Type Reg Imm8Reg) Reg)
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(rule (m_rotl ty src1 src2)
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(decl x64_rotl (Type Reg Imm8Reg) Reg)
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(rule (x64_rotl ty src1 src2)
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(shift_r ty (ShiftKind.RotateLeft) src1 src2))
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;; Helper for creating `rotr` instructions (prefixed with "m_", short for "mach
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;; inst", to disambiguate this from clif's `rotr`).
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(decl m_rotr (Type Reg Imm8Reg) Reg)
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(rule (m_rotr ty src1 src2)
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(decl x64_rotr (Type Reg Imm8Reg) Reg)
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(rule (x64_rotr ty src1 src2)
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(shift_r ty (ShiftKind.RotateRight) src1 src2))
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;; Helper for creating `shl` instructions.
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@@ -326,37 +326,37 @@
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;; And two registers.
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(rule (lower (has_type (fits_in_64 ty) (band x y)))
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(value_reg (m_and ty
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(put_in_reg x)
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(RegMemImm.Reg (put_in_reg y)))))
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(value_reg (x64_and ty
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(put_in_reg x)
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(RegMemImm.Reg (put_in_reg y)))))
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;; And with a memory operand.
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(rule (lower (has_type (fits_in_64 ty)
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(band x (sinkable_load y))))
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(value_reg (m_and ty
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(put_in_reg x)
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(sink_load y))))
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(value_reg (x64_and ty
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(put_in_reg x)
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(sink_load y))))
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(rule (lower (has_type (fits_in_64 ty)
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(band (sinkable_load x) y)))
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(value_reg (m_and ty
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(put_in_reg y)
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(sink_load x))))
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(value_reg (x64_and ty
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(put_in_reg y)
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(sink_load x))))
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;; And with an immediate.
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(rule (lower (has_type (fits_in_64 ty)
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(band x (simm32_from_value y))))
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(value_reg (m_and ty
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(put_in_reg x)
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y)))
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(value_reg (x64_and ty
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(put_in_reg x)
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y)))
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(rule (lower (has_type (fits_in_64 ty)
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(band (simm32_from_value x) y)))
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(value_reg (m_and ty
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(put_in_reg y)
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x)))
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(value_reg (x64_and ty
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(put_in_reg y)
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x)))
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;; SSE.
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@@ -378,8 +378,8 @@
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(y_regs ValueRegs (put_in_regs y))
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(y_lo Reg (value_regs_get y_regs 0))
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(y_hi Reg (value_regs_get y_regs 1)))
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(value_regs (m_and $I64 x_lo (RegMemImm.Reg y_lo))
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(m_and $I64 x_hi (RegMemImm.Reg y_hi)))))
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(value_regs (x64_and $I64 x_lo (RegMemImm.Reg y_lo))
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(x64_and $I64 x_hi (RegMemImm.Reg y_hi)))))
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(rule (lower (has_type $B128 (band x y)))
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;; Booleans are always `0` or `1`, so we only need to do the `and` on the
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@@ -389,7 +389,7 @@
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(x_lo Reg (value_regs_get x_regs 0))
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(x_hi Reg (value_regs_get x_regs 1))
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(y_lo Reg (lo_reg y)))
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(value_regs (m_and $I64 x_lo (RegMemImm.Reg y_lo))
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(value_regs (x64_and $I64 x_lo (RegMemImm.Reg y_lo))
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x_hi)))
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;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
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@@ -832,13 +832,13 @@
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(rule (lower (has_type (ty_8_or_16 ty) (rotl src amt)))
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(let ((amt_ Reg (extend_to_reg amt $I32 (ExtendKind.Zero))))
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(value_reg (m_rotl ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
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(value_reg (x64_rotl ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
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(rule (lower (has_type (ty_8_or_16 ty)
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(rotl src (u64_from_iconst amt))))
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(value_reg (m_rotl ty
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(put_in_reg src)
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(const_to_type_masked_imm8 amt ty))))
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(value_reg (x64_rotl ty
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(put_in_reg src)
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(const_to_type_masked_imm8 amt ty))))
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;; `i64` and `i32`: we can rely on x86's rotate-amount masking since
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;; we operate on the whole register.
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@@ -847,13 +847,13 @@
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;; NB: Only the low bits of `amt` matter since we logically mask the
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;; shift amount to the value's bit width.
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(let ((amt_ Reg (lo_reg amt)))
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(value_reg (m_rotl ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
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(value_reg (x64_rotl ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
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(rule (lower (has_type (ty_32_or_64 ty)
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(rotl src (u64_from_iconst amt))))
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(value_reg (m_rotl ty
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(put_in_reg src)
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(const_to_type_masked_imm8 amt ty))))
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(value_reg (x64_rotl ty
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(put_in_reg src)
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(const_to_type_masked_imm8 amt ty))))
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;; `i128`.
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@@ -872,13 +872,13 @@
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(rule (lower (has_type (ty_8_or_16 ty) (rotr src amt)))
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(let ((amt_ Reg (extend_to_reg amt $I32 (ExtendKind.Zero))))
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(value_reg (m_rotr ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
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(value_reg (x64_rotr ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
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(rule (lower (has_type (ty_8_or_16 ty)
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(rotr src (u64_from_iconst amt))))
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(value_reg (m_rotr ty
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(put_in_reg src)
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(const_to_type_masked_imm8 amt ty))))
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(value_reg (x64_rotr ty
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(put_in_reg src)
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(const_to_type_masked_imm8 amt ty))))
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;; `i64` and `i32`: we can rely on x86's rotate-amount masking since
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;; we operate on the whole register.
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@@ -887,13 +887,13 @@
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;; NB: Only the low bits of `amt` matter since we logically mask the
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;; shift amount to the value's bit width.
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(let ((amt_ Reg (lo_reg amt)))
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(value_reg (m_rotr ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
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(value_reg (x64_rotr ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
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(rule (lower (has_type (ty_32_or_64 ty)
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(rotr src (u64_from_iconst amt))))
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(value_reg (m_rotr ty
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(put_in_reg src)
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(const_to_type_masked_imm8 amt ty))))
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(value_reg (x64_rotr ty
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(put_in_reg src)
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(const_to_type_masked_imm8 amt ty))))
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;; `i128`.
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