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cranelift: Use x64_ prefix to disambiguate with clif in ISLE

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Instead of using `m_` like we used to, which was short for "mach inst" but not
obvious or clear at all.
This commit is contained in:
Nick Fitzgerald
2022-01-13 13:34:55 -08:00
parent a41fdb0303
commit b78731839b
2 changed files with 47 additions and 48 deletions
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27
cranelift/codegen/src/isa/x64/inst.isle
View File

@@ -73,8 +73,7 @@
(src Reg) (src Reg)
(dst WritableReg)) (dst WritableReg))
(LoadEffectiveAddress (addr SyntheticAmode) (LoadEffectiveAddress (addr SyntheticAmode)
(dst WritableReg)) (dst WritableReg))))
))
(type OperandSize extern (type OperandSize extern
(enum Size8 (enum Size8
@@ -534,9 +533,9 @@
(let ((wr WritableReg (temp_writable_reg ty)) (let ((wr WritableReg (temp_writable_reg ty))
(r Reg (writable_reg_to_reg wr)) (r Reg (writable_reg_to_reg wr))
(_ Unit (emit (MInst.XmmRmR (sse_cmp_op $I32X4) (_ Unit (emit (MInst.XmmRmR (sse_cmp_op $I32X4)
r r
(RegMem.Reg r) (RegMem.Reg r)
wr)))) wr))))
r)) r))
;; Helper for creating an SSE register holding an `i64x2` from two `i64` values. ;; Helper for creating an SSE register holding an `i64x2` from two `i64` values.
@@ -697,8 +696,8 @@
;; ;;
;; Use `m_` prefix (short for "mach inst") to disambiguate with the ISLE-builtin ;; Use `m_` prefix (short for "mach inst") to disambiguate with the ISLE-builtin
;; `and` operator. ;; `and` operator.
(decl m_and (Type Reg RegMemImm) Reg) (decl x64_and (Type Reg RegMemImm) Reg)
(rule (m_and ty src1 src2) (rule (x64_and ty src1 src2)
(alu_rmi_r ty (alu_rmi_r ty
(AluRmiROpcode.And) (AluRmiROpcode.And)
src1 src1
@@ -766,9 +765,9 @@
(let ((wr WritableReg (temp_writable_reg ty)) (let ((wr WritableReg (temp_writable_reg ty))
(r Reg (writable_reg_to_reg wr)) (r Reg (writable_reg_to_reg wr))
(_ Unit (emit (MInst.XmmRmR (sse_xor_op ty) (_ Unit (emit (MInst.XmmRmR (sse_xor_op ty)
r r
(RegMem.Reg r) (RegMem.Reg r)
wr)))) wr))))
r)) r))
;; Special case for `f32` zero immediates to use `xorps`. ;; Special case for `f32` zero immediates to use `xorps`.
@@ -807,14 +806,14 @@
;; Helper for creating `rotl` instructions (prefixed with "m_", short for "mach ;; Helper for creating `rotl` instructions (prefixed with "m_", short for "mach
;; inst", to disambiguate this from clif's `rotl`). ;; inst", to disambiguate this from clif's `rotl`).
(decl m_rotl (Type Reg Imm8Reg) Reg) (decl x64_rotl (Type Reg Imm8Reg) Reg)
(rule (m_rotl ty src1 src2) (rule (x64_rotl ty src1 src2)
(shift_r ty (ShiftKind.RotateLeft) src1 src2)) (shift_r ty (ShiftKind.RotateLeft) src1 src2))
;; Helper for creating `rotr` instructions (prefixed with "m_", short for "mach ;; Helper for creating `rotr` instructions (prefixed with "m_", short for "mach
;; inst", to disambiguate this from clif's `rotr`). ;; inst", to disambiguate this from clif's `rotr`).
(decl m_rotr (Type Reg Imm8Reg) Reg) (decl x64_rotr (Type Reg Imm8Reg) Reg)
(rule (m_rotr ty src1 src2) (rule (x64_rotr ty src1 src2)
(shift_r ty (ShiftKind.RotateRight) src1 src2)) (shift_r ty (ShiftKind.RotateRight) src1 src2))
;; Helper for creating `shl` instructions. ;; Helper for creating `shl` instructions.

68
cranelift/codegen/src/isa/x64/lower.isle
View File

@@ -326,37 +326,37 @@
;; And two registers. ;; And two registers.
(rule (lower (has_type (fits_in_64 ty) (band x y))) (rule (lower (has_type (fits_in_64 ty) (band x y)))
(value_reg (m_and ty (value_reg (x64_and ty
(put_in_reg x) (put_in_reg x)
(RegMemImm.Reg (put_in_reg y))))) (RegMemImm.Reg (put_in_reg y)))))
;; And with a memory operand. ;; And with a memory operand.
(rule (lower (has_type (fits_in_64 ty) (rule (lower (has_type (fits_in_64 ty)
(band x (sinkable_load y)))) (band x (sinkable_load y))))
(value_reg (m_and ty (value_reg (x64_and ty
(put_in_reg x) (put_in_reg x)
(sink_load y)))) (sink_load y))))
(rule (lower (has_type (fits_in_64 ty) (rule (lower (has_type (fits_in_64 ty)
(band (sinkable_load x) y))) (band (sinkable_load x) y)))
(value_reg (m_and ty (value_reg (x64_and ty
(put_in_reg y) (put_in_reg y)
(sink_load x)))) (sink_load x))))
;; And with an immediate. ;; And with an immediate.
(rule (lower (has_type (fits_in_64 ty) (rule (lower (has_type (fits_in_64 ty)
(band x (simm32_from_value y)))) (band x (simm32_from_value y))))
(value_reg (m_and ty (value_reg (x64_and ty
(put_in_reg x) (put_in_reg x)
y))) y)))
(rule (lower (has_type (fits_in_64 ty) (rule (lower (has_type (fits_in_64 ty)
(band (simm32_from_value x) y))) (band (simm32_from_value x) y)))
(value_reg (m_and ty (value_reg (x64_and ty
(put_in_reg y) (put_in_reg y)
x))) x)))
;; SSE. ;; SSE.
@@ -378,8 +378,8 @@
(y_regs ValueRegs (put_in_regs y)) (y_regs ValueRegs (put_in_regs y))
(y_lo Reg (value_regs_get y_regs 0)) (y_lo Reg (value_regs_get y_regs 0))
(y_hi Reg (value_regs_get y_regs 1))) (y_hi Reg (value_regs_get y_regs 1)))
(value_regs (m_and $I64 x_lo (RegMemImm.Reg y_lo)) (value_regs (x64_and $I64 x_lo (RegMemImm.Reg y_lo))
(m_and $I64 x_hi (RegMemImm.Reg y_hi))))) (x64_and $I64 x_hi (RegMemImm.Reg y_hi)))))
(rule (lower (has_type $B128 (band x y))) (rule (lower (has_type $B128 (band x y)))
;; Booleans are always `0` or `1`, so we only need to do the `and` on the ;; Booleans are always `0` or `1`, so we only need to do the `and` on the
@@ -389,7 +389,7 @@
(x_lo Reg (value_regs_get x_regs 0)) (x_lo Reg (value_regs_get x_regs 0))
(x_hi Reg (value_regs_get x_regs 1)) (x_hi Reg (value_regs_get x_regs 1))
(y_lo Reg (lo_reg y))) (y_lo Reg (lo_reg y)))
(value_regs (m_and $I64 x_lo (RegMemImm.Reg y_lo)) (value_regs (x64_and $I64 x_lo (RegMemImm.Reg y_lo))
x_hi))) x_hi)))
;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;;;; Rules for `bor` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
@@ -832,13 +832,13 @@
(rule (lower (has_type (ty_8_or_16 ty) (rotl src amt))) (rule (lower (has_type (ty_8_or_16 ty) (rotl src amt)))
(let ((amt_ Reg (extend_to_reg amt $I32 (ExtendKind.Zero)))) (let ((amt_ Reg (extend_to_reg amt $I32 (ExtendKind.Zero))))
(value_reg (m_rotl ty (put_in_reg src) (Imm8Reg.Reg amt_))))) (value_reg (x64_rotl ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
(rule (lower (has_type (ty_8_or_16 ty) (rule (lower (has_type (ty_8_or_16 ty)
(rotl src (u64_from_iconst amt)))) (rotl src (u64_from_iconst amt))))
(value_reg (m_rotl ty (value_reg (x64_rotl ty
(put_in_reg src) (put_in_reg src)
(const_to_type_masked_imm8 amt ty)))) (const_to_type_masked_imm8 amt ty))))
;; `i64` and `i32`: we can rely on x86's rotate-amount masking since ;; `i64` and `i32`: we can rely on x86's rotate-amount masking since
;; we operate on the whole register. ;; we operate on the whole register.
@@ -847,13 +847,13 @@
;; NB: Only the low bits of `amt` matter since we logically mask the ;; NB: Only the low bits of `amt` matter since we logically mask the
;; shift amount to the value's bit width. ;; shift amount to the value's bit width.
(let ((amt_ Reg (lo_reg amt))) (let ((amt_ Reg (lo_reg amt)))
(value_reg (m_rotl ty (put_in_reg src) (Imm8Reg.Reg amt_))))) (value_reg (x64_rotl ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
(rule (lower (has_type (ty_32_or_64 ty) (rule (lower (has_type (ty_32_or_64 ty)
(rotl src (u64_from_iconst amt)))) (rotl src (u64_from_iconst amt))))
(value_reg (m_rotl ty (value_reg (x64_rotl ty
(put_in_reg src) (put_in_reg src)
(const_to_type_masked_imm8 amt ty)))) (const_to_type_masked_imm8 amt ty))))
;; `i128`. ;; `i128`.
@@ -872,13 +872,13 @@
(rule (lower (has_type (ty_8_or_16 ty) (rotr src amt))) (rule (lower (has_type (ty_8_or_16 ty) (rotr src amt)))
(let ((amt_ Reg (extend_to_reg amt $I32 (ExtendKind.Zero)))) (let ((amt_ Reg (extend_to_reg amt $I32 (ExtendKind.Zero))))
(value_reg (m_rotr ty (put_in_reg src) (Imm8Reg.Reg amt_))))) (value_reg (x64_rotr ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
(rule (lower (has_type (ty_8_or_16 ty) (rule (lower (has_type (ty_8_or_16 ty)
(rotr src (u64_from_iconst amt)))) (rotr src (u64_from_iconst amt))))
(value_reg (m_rotr ty (value_reg (x64_rotr ty
(put_in_reg src) (put_in_reg src)
(const_to_type_masked_imm8 amt ty)))) (const_to_type_masked_imm8 amt ty))))
;; `i64` and `i32`: we can rely on x86's rotate-amount masking since ;; `i64` and `i32`: we can rely on x86's rotate-amount masking since
;; we operate on the whole register. ;; we operate on the whole register.
@@ -887,13 +887,13 @@
;; NB: Only the low bits of `amt` matter since we logically mask the ;; NB: Only the low bits of `amt` matter since we logically mask the
;; shift amount to the value's bit width. ;; shift amount to the value's bit width.
(let ((amt_ Reg (lo_reg amt))) (let ((amt_ Reg (lo_reg amt)))
(value_reg (m_rotr ty (put_in_reg src) (Imm8Reg.Reg amt_))))) (value_reg (x64_rotr ty (put_in_reg src) (Imm8Reg.Reg amt_)))))
(rule (lower (has_type (ty_32_or_64 ty) (rule (lower (has_type (ty_32_or_64 ty)
(rotr src (u64_from_iconst amt)))) (rotr src (u64_from_iconst amt))))
(value_reg (m_rotr ty (value_reg (x64_rotr ty
(put_in_reg src) (put_in_reg src)
(const_to_type_masked_imm8 amt ty)))) (const_to_type_masked_imm8 amt ty))))
;; `i128`. ;; `i128`.