Add a return_reg instruction to the base instruction set.

Register-style return is used by all RISC architectures, so it is
natural to have a shared instruction representation.
This commit is contained in:
Jakob Stoklund Olesen
2017-02-21 13:05:17 -08:00
parent 22bc33fa05
commit b6fa40d6a3
6 changed files with 75 additions and 4 deletions

View File

@@ -16,7 +16,7 @@ use cretonne::ir::immediates::{Imm64, Ieee32, Ieee64};
use cretonne::ir::entities::AnyEntity;
use cretonne::ir::instructions::{InstructionFormat, InstructionData, VariableArgs,
TernaryOverflowData, JumpData, BranchData, CallData,
IndirectCallData, ReturnData};
IndirectCallData, ReturnData, ReturnRegData};
use cretonne::isa;
use cretonne::settings;
use testfile::{TestFile, Details, Comment};
@@ -197,6 +197,11 @@ impl Context {
InstructionData::Return { ref mut data, .. } => {
try!(self.map.rewrite_values(&mut data.varargs, loc));
}
InstructionData::ReturnReg { ref mut data, .. } => {
try!(self.map.rewrite_value(&mut data.arg, loc));
try!(self.map.rewrite_values(&mut data.varargs, loc));
}
}
}
}
@@ -1321,6 +1326,19 @@ impl<'a> Parser<'a> {
data: Box::new(ReturnData { varargs: args }),
}
}
InstructionFormat::ReturnReg => {
let raddr = try!(self.match_value("expected SSA value return addr operand"));
try!(self.match_token(Token::Comma, "expected ',' between operands"));
let args = try!(self.parse_value_list());
InstructionData::ReturnReg {
opcode: opcode,
ty: VOID,
data: Box::new(ReturnRegData {
arg: raddr,
varargs: args,
}),
}
}
InstructionFormat::BranchTable => {
let arg = try!(self.match_value("expected SSA value operand"));
try!(self.match_token(Token::Comma, "expected ',' between operands"));