Add a return_reg instruction to the base instruction set.
Register-style return is used by all RISC architectures, so it is natural to have a shared instruction representation.
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@@ -16,7 +16,7 @@ use cretonne::ir::immediates::{Imm64, Ieee32, Ieee64};
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use cretonne::ir::entities::AnyEntity;
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use cretonne::ir::instructions::{InstructionFormat, InstructionData, VariableArgs,
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TernaryOverflowData, JumpData, BranchData, CallData,
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IndirectCallData, ReturnData};
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IndirectCallData, ReturnData, ReturnRegData};
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use cretonne::isa;
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use cretonne::settings;
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use testfile::{TestFile, Details, Comment};
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@@ -197,6 +197,11 @@ impl Context {
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InstructionData::Return { ref mut data, .. } => {
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try!(self.map.rewrite_values(&mut data.varargs, loc));
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}
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InstructionData::ReturnReg { ref mut data, .. } => {
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try!(self.map.rewrite_value(&mut data.arg, loc));
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try!(self.map.rewrite_values(&mut data.varargs, loc));
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}
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}
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}
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}
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@@ -1321,6 +1326,19 @@ impl<'a> Parser<'a> {
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data: Box::new(ReturnData { varargs: args }),
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}
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}
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InstructionFormat::ReturnReg => {
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let raddr = try!(self.match_value("expected SSA value return addr operand"));
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try!(self.match_token(Token::Comma, "expected ',' between operands"));
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let args = try!(self.parse_value_list());
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InstructionData::ReturnReg {
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opcode: opcode,
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ty: VOID,
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data: Box::new(ReturnRegData {
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arg: raddr,
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varargs: args,
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}),
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}
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}
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InstructionFormat::BranchTable => {
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let arg = try!(self.match_value("expected SSA value operand"));
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try!(self.match_token(Token::Comma, "expected ',' between operands"));
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