Revert IR changes

Along with the x64 and s390x changes. Now pattern matching the
uextend(atomic_load) in the aarch64 backend.

cranelift/filetests/filetests/isa/aarch64/atomic_load.clif

@@ -21,50 +21,75 @@ block0(v0: i64):
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
 
-function %atomic_uload_i32_i64(i64) -> i64 {
+function %atomic_load_i16(i64) -> i16 {
 block0(v0: i64):
-  v1 = atomic_uload32.i64 v0
+  v1 = atomic_load.i16 v0
   return v1
 }
 
+; check: ldarh w0, [x0]
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %atomic_load_i8(i64) -> i8 {
+block0(v0: i64):
+  v1 = atomic_load.i8 v0
+  return v1
+}
+
+; check: ldarb w0, [x0]
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %atomic_load_i32_i64(i64) -> i64 {
+block0(v0: i64):
+  v1 = atomic_load.i32 v0
+  v2 = uextend.i64 v1
+  return v2
+}
+
 ; check: ldar w0, [x0]
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
 
-function %atomic_uload_i16_i32(i64) -> i32 {
+function %atomic_load_i16_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = atomic_uload16.i32 v0
-  return v1
+  v1 = atomic_load.i16 v0
+  v2 = uextend.i64 v1
+  return v2
 }
 
 ; check: ldarh w0, [x0]
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
 
-function %atomic_uload_i16_i64(i64) -> i64 {
+function %atomic_load_i8_i64(i64) -> i64 {
 block0(v0: i64):
-  v1 = atomic_uload16.i64 v0
-  return v1
+  v1 = atomic_load.i8 v0
+  v2 = uextend.i64 v1
+  return v2
+}
+
+; check: ldarb w0, [x0]
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %atomic_load_i16_i32(i64) -> i32 {
+block0(v0: i64):
+  v1 = atomic_load.i16 v0
+  v2 = uextend.i32 v1
+  return v2
 }
 
 ; check: ldarh w0, [x0]
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
 
-function %atomic_uload_i8_i32(i64) -> i32 {
+function %atomic_load_i8_i32(i64) -> i32 {
 block0(v0: i64):
-  v1 = atomic_uload8.i32 v0
-  return v1
-}
-
-; check: ldarb w0, [x0]
-; nextln: ldp fp, lr, [sp], #16
-; nextln: ret
-
-function %atomic_uload_i8_i64(i64) -> i64 {
-block0(v0: i64):
-  v1 = atomic_uload8.i64 v0
-  return v1
+  v1 = atomic_load.i8 v0
+  v2 = uextend.i32 v1
+  return v2
 }
 
 ; check: ldarb w0, [x0]

cranelift/filetests/filetests/isa/aarch64/atomic_store.clif

@@ -21,52 +21,82 @@ block0(v0: i32, v1: i64):
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
 
-function %atomic_ustore_i32_i64(i64, i64) {
-block0(v0: i64, v1: i64):
-  atomic_store32.i64 v0, v1
+function %atomic_store_i16(i16, i64) {
+block0(v0: i16, v1: i64):
+  atomic_store.i16 v0, v1
   return
 }
 
+; check: stlrh w0, [x1]
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %atomic_store_i8(i8, i64) {
+block0(v0: i8, v1: i64):
+  atomic_store.i8 v0, v1
+  return
+}
+
+; check: stlrb w0, [x1]
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %atomic_store_i64_i32(i64, i64) {
+block0(v0: i64, v1: i64):
+  v2 = ireduce.i32 v0
+  atomic_store.i32 v2, v1
+  return
+}
+
+; check-not: uxt
 ; check: stlr w0, [x1]
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
 
-function %atomic_ustore_i16_i32(i32, i64) {
-block0(v0: i32, v1: i64):
-  atomic_store16.i32 v0, v1
+function %atomic_store_i64_i16(i64, i64) {
+block0(v0: i64, v1: i64):
+  v2 = ireduce.i16 v0
+  atomic_store.i16 v2, v1
   return
 }
 
+; check-not: uxt
 ; check: stlrh w0, [x1]
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
 
-function %atomic_ustore_i16_i64(i64, i64) {
+function %atomic_store_i64_i8(i64, i64) {
 block0(v0: i64, v1: i64):
-  atomic_store16.i64 v0, v1
+  v2 = ireduce.i8 v0
+  atomic_store.i8 v2, v1
   return
 }
 
+; check-not: uxt
+; check: stlrb w0, [x1]
+; nextln: ldp fp, lr, [sp], #16
+; nextln: ret
+
+function %atomic_store_i32_i16(i32, i64) {
+block0(v0: i32, v1: i64):
+  v2 = ireduce.i16 v0
+  atomic_store.i16 v2, v1
+  return
+}
+
+; check-not: uxt
 ; check: stlrh w0, [x1]
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret
 
-function %atomic_ustore_i8_i32(i32, i64) {
+function %atomic_store_i32_i8(i32, i64) {
 block0(v0: i32, v1: i64):
-  atomic_store8.i32 v0, v1
-  return
-}
-
-; check: stlrb w0, [x1]
-; nextln: ldp fp, lr, [sp], #16
-; nextln: ret
-
-function %atomic_ustore_i8_i64(i64, i64) {
-block0(v0: i64, v1: i64):
-  atomic_store8.i64 v0, v1
+  v2 = ireduce.i8 v0
+  atomic_store.i8 v2, v1
   return
 }
 
+; check-not: uxt
 ; check: stlrb w0, [x1]
 ; nextln: ldp fp, lr, [sp], #16
 ; nextln: ret