Revert IR changes

Along with the x64 and s390x changes. Now pattern matching the
uextend(atomic_load) in the aarch64 backend.

cranelift/codegen/src/isa/aarch64/lower.rs

@@ -1740,6 +1740,22 @@ pub(crate) fn is_valid_atomic_transaction_ty(ty: Type) -> bool {
     }
 }
 
+pub(crate) fn emit_atomic_load<C: LowerCtx<I = Inst>>(
+    ctx: &mut C,
+    rt: Writable<Reg>,
+    insn: IRInst,
+) {
+    assert!(ctx.data(insn).opcode() == Opcode::AtomicLoad);
+    let inputs = insn_inputs(ctx, insn);
+    let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
+    let access_ty = ctx.output_ty(insn, 0);
+    assert!(is_valid_atomic_transaction_ty(access_ty));
+    // We're ignoring the result type of the load because the LoadAcquire will
+    // explicitly zero extend to the nearest word, and also zero the high half
+    // of an X register.
+    ctx.emit(Inst::LoadAcquire { access_ty, rt, rn });
+}
+
 fn load_op_to_ty(op: Opcode) -> Option<Type> {
     match op {
         Opcode::Sload8 | Opcode::Uload8 | Opcode::Sload8Complex | Opcode::Uload8Complex => Some(I8),