From b61e6783094996b2fa62d7132c6a068b30437ad7 Mon Sep 17 00:00:00 2001
From: Ulrich Weigand <ulrich.weigand@de.ibm.com>
Date: Tue, 25 Oct 2022 20:04:31 +0200
Subject: [PATCH] s390x: Fix more regalloc checker errors (#5121)

For VecInsertLane[Undef] and VecExtractLane, if lane_reg is zero_reg(),
the instruction does not actually use any register value.

Fixes https://github.com/bytecodealliance/wasmtime/issues/5090
---
 cranelift/codegen/src/isa/s390x/inst/mod.rs | 12 +++++++++---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/cranelift/codegen/src/isa/s390x/inst/mod.rs b/cranelift/codegen/src/isa/s390x/inst/mod.rs
index 706c50d4d9..8e3e4eda57 100644
--- a/cranelift/codegen/src/isa/s390x/inst/mod.rs
+++ b/cranelift/codegen/src/isa/s390x/inst/mod.rs
@@ -974,21 +974,27 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
             collector.reg_reuse_def(rd, 1);
             collector.reg_use(ri);
             collector.reg_use(rn);
-            collector.reg_use(lane_reg);
+            if lane_reg != zero_reg() {
+                collector.reg_use(lane_reg);
+            }
         }
         &Inst::VecInsertLaneUndef {
             rd, rn, lane_reg, ..
         } => {
             collector.reg_def(rd);
             collector.reg_use(rn);
-            collector.reg_use(lane_reg);
+            if lane_reg != zero_reg() {
+                collector.reg_use(lane_reg);
+            }
         }
         &Inst::VecExtractLane {
             rd, rn, lane_reg, ..
         } => {
             collector.reg_def(rd);
             collector.reg_use(rn);
-            collector.reg_use(lane_reg);
+            if lane_reg != zero_reg() {
+                collector.reg_use(lane_reg);
+            }
         }
         &Inst::VecInsertLaneImm { rd, ri, .. } => {
             collector.reg_reuse_def(rd, 1);