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Improve code generation for floating-point constants

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Copyright (c) 2022, Arm Limited.
This commit is contained in:
Freddie Liardet
2021-12-02 15:38:15 +00:00
parent 06a7bfdcbd
commit b5531580e7
10 changed files with 490 additions and 309 deletions
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121
cranelift/filetests/filetests/isa/aarch64/constants.clif
View File

@@ -292,3 +292,124 @@ block0:
; Inst 1: ret
; }}
function %f() -> f64 {
block0:
v0 = f64const 0x1.0
return v0
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 2)
; Inst 0: fmov d0, #1
; Inst 1: ret
; }}
function %f() -> f32 {
block0:
v0 = f32const 0x5.0
return v0
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 2)
; Inst 0: fmov s0, #5
; Inst 1: ret
; }}
function %f() -> f64 {
block0:
v0 = f64const 0x32.0
return v0
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 3)
; Inst 0: movz x0, #16457, LSL #48
; Inst 1: fmov d0, x0
; Inst 2: ret
; }}
function %f() -> f32 {
block0:
v0 = f32const 0x32.0
return v0
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 3)
; Inst 0: movz x0, #16968, LSL #16
; Inst 1: fmov s0, w0
; Inst 2: ret
; }}
function %f() -> f64 {
block0:
v0 = f64const 0x0.0
return v0
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 2)
; Inst 0: movi v0.2s, #0
; Inst 1: ret
; }}
function %f() -> f32 {
block0:
v0 = f32const 0x0.0
return v0
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 2)
; Inst 0: movi v0.2s, #0
; Inst 1: ret
; }}
function %f() -> f64 {
block0:
v0 = f64const -0x10.0
return v0
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 2)
; Inst 0: fmov d0, #-16
; Inst 1: ret
; }}
function %f() -> f32 {
block0:
v0 = f32const -0x10.0
return v0
}
; VCode_ShowWithRRU {{
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 2)
; Inst 0: fmov s0, #-16
; Inst 1: ret
; }}

84
cranelift/filetests/filetests/isa/aarch64/fcvt-small.clif
View File

@@ -76,19 +76,18 @@ block0(v0: f32):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 12)
; (instruction range: 0 .. 11)
; Inst 0: fcmp s0, s0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #49024, LSL #16
; Inst 3: fmov d1, x0
; Inst 4: fcmp s0, s1
; Inst 5: b.gt 8 ; udf
; Inst 6: movz x0, #17280, LSL #16
; Inst 7: fmov d1, x0
; Inst 8: fcmp s0, s1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzu w0, s0
; Inst 11: ret
; Inst 2: fmov s1, #-1
; Inst 3: fcmp s0, s1
; Inst 4: b.gt 8 ; udf
; Inst 5: movz x0, #17280, LSL #16
; Inst 6: fmov s1, w0
; Inst 7: fcmp s0, s1
; Inst 8: b.mi 8 ; udf
; Inst 9: fcvtzu w0, s0
; Inst 10: ret
; }}
function u0:0(f64) -> i8 {
@@ -101,19 +100,18 @@ block0(v0: f64):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 12)
; (instruction range: 0 .. 11)
; Inst 0: fcmp d0, d0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #49136, LSL #48
; Inst 3: fmov d1, x0
; Inst 4: fcmp d0, d1
; Inst 5: b.gt 8 ; udf
; Inst 6: movz x0, #16496, LSL #48
; Inst 7: fmov d1, x0
; Inst 8: fcmp d0, d1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzu w0, d0
; Inst 11: ret
; Inst 2: fmov d1, #-1
; Inst 3: fcmp d0, d1
; Inst 4: b.gt 8 ; udf
; Inst 5: movz x0, #16496, LSL #48
; Inst 6: fmov d1, x0
; Inst 7: fcmp d0, d1
; Inst 8: b.mi 8 ; udf
; Inst 9: fcvtzu w0, d0
; Inst 10: ret
; }}
function u0:0(f32) -> i16 {
@@ -126,19 +124,18 @@ block0(v0: f32):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 12)
; (instruction range: 0 .. 11)
; Inst 0: fcmp s0, s0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #49024, LSL #16
; Inst 3: fmov d1, x0
; Inst 4: fcmp s0, s1
; Inst 5: b.gt 8 ; udf
; Inst 6: movz x0, #18304, LSL #16
; Inst 7: fmov d1, x0
; Inst 8: fcmp s0, s1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzu w0, s0
; Inst 11: ret
; Inst 2: fmov s1, #-1
; Inst 3: fcmp s0, s1
; Inst 4: b.gt 8 ; udf
; Inst 5: movz x0, #18304, LSL #16
; Inst 6: fmov s1, w0
; Inst 7: fcmp s0, s1
; Inst 8: b.mi 8 ; udf
; Inst 9: fcvtzu w0, s0
; Inst 10: ret
; }}
function u0:0(f64) -> i16 {
@@ -151,18 +148,17 @@ block0(v0: f64):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 12)
; (instruction range: 0 .. 11)
; Inst 0: fcmp d0, d0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #49136, LSL #48
; Inst 3: fmov d1, x0
; Inst 4: fcmp d0, d1
; Inst 5: b.gt 8 ; udf
; Inst 6: movz x0, #16624, LSL #48
; Inst 7: fmov d1, x0
; Inst 8: fcmp d0, d1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzu w0, d0
; Inst 11: ret
; Inst 2: fmov d1, #-1
; Inst 3: fcmp d0, d1
; Inst 4: b.gt 8 ; udf
; Inst 5: movz x0, #16624, LSL #48
; Inst 6: fmov d1, x0
; Inst 7: fcmp d0, d1
; Inst 8: b.mi 8 ; udf
; Inst 9: fcvtzu w0, d0
; Inst 10: ret
; }}

104
cranelift/filetests/filetests/isa/aarch64/floating-point.clif
View File

@@ -494,19 +494,18 @@ block0(v0: f32):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 12)
; (instruction range: 0 .. 11)
; Inst 0: fcmp s0, s0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #49024, LSL #16
; Inst 3: fmov d1, x0
; Inst 4: fcmp s0, s1
; Inst 5: b.gt 8 ; udf
; Inst 6: movz x0, #20352, LSL #16
; Inst 7: fmov d1, x0
; Inst 8: fcmp s0, s1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzu w0, s0
; Inst 11: ret
; Inst 2: fmov s1, #-1
; Inst 3: fcmp s0, s1
; Inst 4: b.gt 8 ; udf
; Inst 5: movz x0, #20352, LSL #16
; Inst 6: fmov s1, w0
; Inst 7: fcmp s0, s1
; Inst 8: b.mi 8 ; udf
; Inst 9: fcvtzu w0, s0
; Inst 10: ret
; }}
function %f34(f32) -> i32 {
@@ -523,11 +522,11 @@ block0(v0: f32):
; Inst 0: fcmp s0, s0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #52992, LSL #16
; Inst 3: fmov d1, x0
; Inst 3: fmov s1, w0
; Inst 4: fcmp s0, s1
; Inst 5: b.ge 8 ; udf
; Inst 6: movz x0, #20224, LSL #16
; Inst 7: fmov d1, x0
; Inst 7: fmov s1, w0
; Inst 8: fcmp s0, s1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzs w0, s0
@@ -544,19 +543,18 @@ block0(v0: f32):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 12)
; (instruction range: 0 .. 11)
; Inst 0: fcmp s0, s0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #49024, LSL #16
; Inst 3: fmov d1, x0
; Inst 4: fcmp s0, s1
; Inst 5: b.gt 8 ; udf
; Inst 6: movz x0, #24448, LSL #16
; Inst 7: fmov d1, x0
; Inst 8: fcmp s0, s1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzu x0, s0
; Inst 11: ret
; Inst 2: fmov s1, #-1
; Inst 3: fcmp s0, s1
; Inst 4: b.gt 8 ; udf
; Inst 5: movz x0, #24448, LSL #16
; Inst 6: fmov s1, w0
; Inst 7: fcmp s0, s1
; Inst 8: b.mi 8 ; udf
; Inst 9: fcvtzu x0, s0
; Inst 10: ret
; }}
function %f36(f32) -> i64 {
@@ -573,11 +571,11 @@ block0(v0: f32):
; Inst 0: fcmp s0, s0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #57088, LSL #16
; Inst 3: fmov d1, x0
; Inst 3: fmov s1, w0
; Inst 4: fcmp s0, s1
; Inst 5: b.ge 8 ; udf
; Inst 6: movz x0, #24320, LSL #16
; Inst 7: fmov d1, x0
; Inst 7: fmov s1, w0
; Inst 8: fcmp s0, s1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzs x0, s0
@@ -594,19 +592,18 @@ block0(v0: f64):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 12)
; (instruction range: 0 .. 11)
; Inst 0: fcmp d0, d0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #49136, LSL #48
; Inst 3: fmov d1, x0
; Inst 4: fcmp d0, d1
; Inst 5: b.gt 8 ; udf
; Inst 6: movz x0, #16880, LSL #48
; Inst 7: fmov d1, x0
; Inst 8: fcmp d0, d1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzu w0, d0
; Inst 11: ret
; Inst 2: fmov d1, #-1
; Inst 3: fcmp d0, d1
; Inst 4: b.gt 8 ; udf
; Inst 5: movz x0, #16880, LSL #48
; Inst 6: fmov d1, x0
; Inst 7: fcmp d0, d1
; Inst 8: b.mi 8 ; udf
; Inst 9: fcvtzu w0, d0
; Inst 10: ret
; }}
function %f38(f64) -> i32 {
@@ -643,19 +640,18 @@ block0(v0: f64):
; Entry block: 0
; Block 0:
; (original IR block: block0)
; (instruction range: 0 .. 12)
; (instruction range: 0 .. 11)
; Inst 0: fcmp d0, d0
; Inst 1: b.vc 8 ; udf
; Inst 2: movz x0, #49136, LSL #48
; Inst 3: fmov d1, x0
; Inst 4: fcmp d0, d1
; Inst 5: b.gt 8 ; udf
; Inst 6: movz x0, #17392, LSL #48
; Inst 7: fmov d1, x0
; Inst 8: fcmp d0, d1
; Inst 9: b.mi 8 ; udf
; Inst 10: fcvtzu x0, d0
; Inst 11: ret
; Inst 2: fmov d1, #-1
; Inst 3: fcmp d0, d1
; Inst 4: b.gt 8 ; udf
; Inst 5: movz x0, #17392, LSL #48
; Inst 6: fmov d1, x0
; Inst 7: fcmp d0, d1
; Inst 8: b.mi 8 ; udf
; Inst 9: fcvtzu x0, d0
; Inst 10: ret
; }}
function %f40(f64) -> i64 {
@@ -815,7 +811,7 @@ block0(v0: f32):
; (original IR block: block0)
; (instruction range: 0 .. 9)
; Inst 0: movz x0, #20352, LSL #16
; Inst 1: fmov d1, x0
; Inst 1: fmov s1, w0
; Inst 2: fmin s2, s0, s1
; Inst 3: movi v1.2s, #0
; Inst 4: fmax s2, s2, s1
@@ -837,10 +833,10 @@ block0(v0: f32):
; (original IR block: block0)
; (instruction range: 0 .. 11)
; Inst 0: movz x0, #20224, LSL #16
; Inst 1: fmov d1, x0
; Inst 1: fmov s1, w0
; Inst 2: fmin s1, s0, s1
; Inst 3: movz x0, #52992, LSL #16
; Inst 4: fmov d2, x0
; Inst 4: fmov s2, w0
; Inst 5: fmax s1, s1, s2
; Inst 6: movi v2.2s, #0
; Inst 7: fcmp s0, s0
@@ -861,7 +857,7 @@ block0(v0: f32):
; (original IR block: block0)
; (instruction range: 0 .. 9)
; Inst 0: movz x0, #24448, LSL #16
; Inst 1: fmov d1, x0
; Inst 1: fmov s1, w0
; Inst 2: fmin s2, s0, s1
; Inst 3: movi v1.2s, #0
; Inst 4: fmax s2, s2, s1
@@ -883,10 +879,10 @@ block0(v0: f32):
; (original IR block: block0)
; (instruction range: 0 .. 11)
; Inst 0: movz x0, #24320, LSL #16
; Inst 1: fmov d1, x0
; Inst 1: fmov s1, w0
; Inst 2: fmin s1, s0, s1
; Inst 3: movz x0, #57088, LSL #16
; Inst 4: fmov d2, x0
; Inst 4: fmov s2, w0
; Inst 5: fmax s1, s1, s2
; Inst 6: movi v2.2s, #0
; Inst 7: fcmp s0, s0