Add a section about implementation limits.
Fix a few other minor issues with the documentation.
This commit is contained in:
@@ -58,7 +58,7 @@ html:
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@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
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@echo "Build finished. The HTML pages are in $(BUILDDIR)/html."
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autohtml: html
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autohtml: html
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$(SPHINXABUILD) -z ../lib/cretonne/meta --ignore '*.swp' -b html -E $(ALLSPHINXOPTS) $(BUILDDIR)/html
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$(SPHINXABUILD) -z ../lib/cretonne/meta --ignore '.*.sw?' -b html -E $(ALLSPHINXOPTS) $(BUILDDIR)/html
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dirhtml:
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dirhtml:
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$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
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$(SPHINXBUILD) -b dirhtml $(ALLSPHINXOPTS) $(BUILDDIR)/dirhtml
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@@ -80,7 +80,7 @@ into Cretonne :term:`IL` contains multiple assignments to the same variables.
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Such variables can be presented to Cretonne as :term:`stack slot`\s instead.
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Such variables can be presented to Cretonne as :term:`stack slot`\s instead.
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Stack slots are accessed with the :inst:`stack_store` and :inst:`stack_load`
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Stack slots are accessed with the :inst:`stack_store` and :inst:`stack_load`
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instructions which behave more like variable accesses in a typical programming
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instructions which behave more like variable accesses in a typical programming
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language. Cretonne can perform the necessary dataflow analysis to convert stack
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language. Cretonne can perform the necessary data-flow analysis to convert stack
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slots to SSA form.
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slots to SSA form.
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.. _value-types:
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.. _value-types:
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@@ -459,7 +459,7 @@ accesses may trap, or they may work. Sometimes, operating systems catch
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alignment traps and emulate the misaligned memory access.
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alignment traps and emulate the misaligned memory access.
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On target architectures like x86 that don't check alignment, Cretonne expands
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On target architectures like x86 that don't check alignment, Cretonne expands
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the aligntrap flag into a conditional trap instruction::
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the `aligntrap` flag into a conditional trap instruction::
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v5 = load.i32 v1, 4, align(4), aligntrap
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v5 = load.i32 v1, 4, align(4), aligntrap
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; Becomes:
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; Becomes:
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@@ -854,6 +854,45 @@ group.
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Target ISAs may define further instructions in their own instruction groups.
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Target ISAs may define further instructions in their own instruction groups.
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Implementation limits
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=====================
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Cretonne's intermediate representation imposes some limits on the size of
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functions and the number of entities allowed. If these limits are exceeded, the
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implementation will panic.
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Number of instructions in a function
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At most :math:`2^{31} - 1`.
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Number of EBBs in a function
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At most :math:`2^{31} - 1`.
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Every EBB needs at least a terminator instruction anyway.
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Number of secondary values in a function
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At most :math:`2^{31} - 1`.
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Secondary values are any SSA values that are not the first result of an
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instruction.
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Other entities declared in the preamble
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At most :math:`2^{32} - 1`.
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This covers things like stack slots, jump tables, external functions, and
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function signatures, etc.
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Number of arguments to an EBB
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At most :math:`2^{16}`.
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Number of arguments to a function
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At most :math:`2^{16}`.
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This follows from the limit on arguments to the entry EBB. Note that
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Cretonne may add a handful of ABI register arguments as function signatures
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are lowered. This is for representing things like the link register, the
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incoming frame pointer, and callee-saved registers that are saved in the
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prologue.
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Glossary
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Glossary
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========
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========
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@@ -1,6 +1,6 @@
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"""
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"""
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ARM 32-bit Architecture
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ARM 32-bit Architecture
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----------------------
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-----------------------
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This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
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This target ISA generates code for ARMv7 and ARMv8 CPUs in 32-bit mode
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(AArch32). We support both ARM and Thumb2 instruction encodings.
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(AArch32). We support both ARM and Thumb2 instruction encodings.
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