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x64: Port fdemote and fvdemote to ISLE (#4449)

Browse Source 
https://github.com/bytecodealliance/wasmtime/pull/4449
This commit is contained in:
Trevor Elliott
2022-07-18 14:26:23 -07:00
committed by GitHub
parent 638dc4e0b3
commit b519c975cb
4 changed files with 115 additions and 37 deletions
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14
cranelift/codegen/src/isa/x64/inst.isle
View File

@@ -2841,6 +2841,13 @@
(_ Unit (emit (MInst.XmmUnaryRmR (SseOpcode.Cvtss2sd) x dst))))
dst))
;; Helper for creating `cvtsd2ss` instructions.
(decl x64_cvtsd2ss (Xmm) Xmm)
(rule (x64_cvtsd2ss x)
(let ((dst WritableXmm (temp_writable_xmm))
(_ Unit (emit (MInst.XmmUnaryRmR (SseOpcode.Cvtsd2ss) x dst))))
dst))
;; Helper for creating `cvtps2pd` instructions.
(decl x64_cvtps2pd (Xmm) Xmm)
(rule (x64_cvtps2pd x)
@@ -2848,6 +2855,13 @@
(_ Unit (emit (MInst.XmmUnaryRmR (SseOpcode.Cvtps2pd) x dst))))
dst))
;; Helper for creating `cvtpd2ps` instructions.
(decl x64_cvtpd2ps (Xmm) Xmm)
(rule (x64_cvtpd2ps x)
(let ((dst WritableXmm (temp_writable_xmm))
(_ Unit (emit (MInst.XmmUnaryRmR (SseOpcode.Cvtpd2ps) x dst))))
dst))
;; Helpers for creating `pcmpeq*` instructions.
(decl x64_pcmpeq (Type Xmm XmmMem) Xmm)
(rule (x64_pcmpeq $I8X16 x y) (x64_pcmpeqb x y))

8
cranelift/codegen/src/isa/x64/lower.isle
View File

@@ -2351,6 +2351,14 @@
(rule (lower (has_type $F64X2 (fvpromote_low x)))
(x64_cvtps2pd (put_in_xmm x)))
;; Rules for `fdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $F32 (fdemote x)))
(x64_cvtsd2ss x))
;; Rules for `fvdemote` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $F32X4 (fvdemote x)))
(x64_cvtpd2ps x))
;; Rules for `fmin` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
(rule (lower (has_type $F32 (fmin x y)))

45
cranelift/codegen/src/isa/x64/lower.rs
View File

@@ -893,13 +893,14 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
| Opcode::Fmin
| Opcode::Fmax
| Opcode::FminPseudo
| Opcode::FmaxPseudo => implemented_in_isle(ctx),
Opcode::Icmp => {
implemented_in_isle(ctx);
}
Opcode::Fcmp => {
| Opcode::FmaxPseudo
| Opcode::Sqrt
| Opcode::Fpromote
| Opcode::FvpromoteLow
| Opcode::Fdemote
| Opcode::Fvdemote
| Opcode::Icmp
| Opcode::Fcmp => {
implemented_in_isle(ctx);
}
@@ -1020,36 +1021,6 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
};
}
Opcode::Sqrt => {
implemented_in_isle(ctx);
}
Opcode::Fpromote => {
implemented_in_isle(ctx);
}
Opcode::FvpromoteLow => {
implemented_in_isle(ctx);
}
Opcode::Fdemote => {
// We can't guarantee the RHS (if a load) is 128-bit aligned, so we
// must avoid merging a load here.
let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
ctx.emit(Inst::xmm_unary_rm_r(SseOpcode::Cvtsd2ss, src, dst));
}
Opcode::Fvdemote => {
let src = RegMem::reg(put_input_in_reg(ctx, inputs[0]));
let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
ctx.emit(Inst::xmm_unary_rm_r(
SseOpcode::Cvtpd2ps,
RegMem::from(src),
dst,
));
}
Opcode::FcvtFromSint => {
let output_ty = ty.unwrap();
if !output_ty.is_vector() {