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Remove SSE2 setting for x86

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In talking to @sunfishcode, he preferred to avoid the confusion of more ISA predicates by eliminating SSE2. SSE2 was released with the Pentium 4 in 2000 so it is unlikely that current CPUs would have SIMD enabled and not have this feature. I tried to note the SSE2-specific instructions with comments in the code.
This commit is contained in:
Andrew Brown
2019-07-17 09:45:58 -07:00
committed by Dan Gohman
parent 6605f308b3
commit b4ef90cfcd
5 changed files with 53 additions and 33 deletions
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9
cranelift/codegen/meta/src/isa/x86/settings.rs
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@@ -3,9 +3,6 @@ use crate::cdsl::settings::{PredicateNode, SettingGroup, SettingGroupBuilder};
pub fn define(shared: &SettingGroup) -> SettingGroup {
let mut settings = SettingGroupBuilder::new("x86");
// CPUID.01H:EDX
let has_sse2 = settings.add_bool("has_sse2", "SSE2: CPUID.01H:EDX.SSE2[bit 26]", false);
// CPUID.01H:ECX
let has_sse3 = settings.add_bool("has_sse3", "SSE3: CPUID.01H:ECX.SSE3[bit 0]", false);
let has_ssse3 = settings.add_bool("has_ssse3", "SSSE3: CPUID.01H:ECX.SSSE3[bit 9]", false);
@@ -35,7 +32,6 @@ pub fn define(shared: &SettingGroup) -> SettingGroup {
let shared_enable_simd = shared.get_bool("enable_simd");
settings.add_predicate("use_sse2", predicate!(shared_enable_simd && has_sse2));
settings.add_predicate("use_ssse3", predicate!(shared_enable_simd && has_ssse3));
settings.add_predicate("use_sse41", predicate!(shared_enable_simd && has_sse41));
settings.add_predicate(
@@ -69,7 +65,7 @@ pub fn define(shared: &SettingGroup) -> SettingGroup {
settings.add_preset("baseline", preset!());
let nehalem = settings.add_preset(
"nehalem",
preset!(has_sse2 && has_sse3 && has_ssse3 && has_sse41 && has_sse42 && has_popcnt),
preset!(has_sse3 && has_ssse3 && has_sse41 && has_sse42 && has_popcnt),
);
let haswell = settings.add_preset(
"haswell",
@@ -82,8 +78,7 @@ pub fn define(shared: &SettingGroup) -> SettingGroup {
settings.add_preset(
"znver1",
preset!(
has_sse2
&& has_sse3
has_sse3
&& has_ssse3
&& has_sse41
&& has_sse42