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Remove vconcat and vsplit clif instructions (#5465)

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Fixes #5463.

* remove vsplit instruction

* remove vconcat instruction

* remove unsused half/double vector helper functions

* remove unused operand constraints

* delete + inline Type::half_vector method
This commit is contained in:
Ayomide Bamidele
2022-12-20 00:41:55 +00:00
committed by GitHub
parent 307945877e
commit b47e644c3d
6 changed files with 7 additions and 148 deletions
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12
cranelift/codegen/src/ir/instructions.rs
View File

@@ -603,12 +603,6 @@ enum OperandConstraint {
/// This operand is `ctrlType.double_width()`.
DoubleWidth,
/// This operand is `ctrlType.half_vector()`.
HalfVector,
/// This operand is `ctrlType.double_vector()`.
DoubleVector,
/// This operand is `ctrlType.split_lanes()`.
SplitLanes,
@@ -637,12 +631,6 @@ impl OperandConstraint {
.double_width()
.expect("invalid type for double_width"),
),
HalfVector => Bound(
ctrl_type
.half_vector()
.expect("invalid type for half_vector"),
),
DoubleVector => Bound(ctrl_type.by(2).expect("invalid type for double_vector")),
SplitLanes => {
if ctrl_type.is_dynamic_vector() {
Bound(

24
cranelift/codegen/src/ir/types.rs
View File

@@ -364,17 +364,6 @@ impl Type {
Some(Self(self.0 - constants::VECTOR_BASE))
}
/// Get a SIMD vector with half the number of lanes.
///
/// There is no `double_vector()` method. Use `t.by(2)` instead.
pub fn half_vector(self) -> Option<Self> {
if self.is_vector() && !self.is_dynamic_vector() {
Some(Self(self.0 - 0x10))
} else {
None
}
}
/// Split the lane width in half and double the number of lanes to maintain the same bit-width.
///
/// If this is a scalar type of `n` bits, it produces a SIMD vector type of `(n/2)x2`.
@@ -391,7 +380,13 @@ impl Type {
/// If this is a scalar type, it will return `None`.
pub fn merge_lanes(self) -> Option<Self> {
match self.double_width() {
Some(double_width) => double_width.half_vector(),
Some(double_width) => {
if double_width.is_vector() && !double_width.is_dynamic_vector() {
Some(Self(double_width.0 - 0x10))
} else {
None
}
}
None => None,
}
}
@@ -544,10 +539,6 @@ mod tests {
assert_eq!(big.lane_count(), 256);
assert_eq!(big.bits(), 64 * 256);
assert_eq!(big.half_vector().unwrap().to_string(), "f64x128");
assert_eq!(I32.half_vector(), None);
assert_eq!(INVALID.half_vector(), None);
// Check that the generated constants match the computed vector types.
assert_eq!(I32.by(4), Some(I32X4));
assert_eq!(F64.by(8), Some(F64X8));
@@ -566,7 +557,6 @@ mod tests {
assert_eq!(I16X8XN.min_lane_count(), 8);
// Change lane counts
assert_eq!(F64X4XN.half_vector(), None);
assert_eq!(I8X8XN.by(2), None);
// Conversions to and from vectors.