From b448574a49d6a1bc56fa8f9b5397720cf2d4392e Mon Sep 17 00:00:00 2001
From: Dimo <lami4ka@gmail.com>
Date: Mon, 24 Jul 2017 13:41:04 -0700
Subject: [PATCH] Assert all InstructionGroups are closed in
 TargetIsa.__init__(); Close x86 group

---
 lib/cretonne/meta/cdsl/isa.py               | 5 +++++
 lib/cretonne/meta/isa/intel/instructions.py | 2 ++
 2 files changed, 7 insertions(+)

diff --git a/lib/cretonne/meta/cdsl/isa.py b/lib/cretonne/meta/cdsl/isa.py
index ea10c64640..29a3698304 100644
--- a/lib/cretonne/meta/cdsl/isa.py
+++ b/lib/cretonne/meta/cdsl/isa.py
@@ -5,6 +5,7 @@ from .predicates import And
 from .registers import RegClass, Register, Stack
 from .ast import Apply
 from .types import ValueType
+from .instructions import InstructionGroup
 
 # The typing module is only required by mypy, and we don't use these imports
 # outside type comments.
@@ -47,6 +48,10 @@ class TargetISA(object):
         self.regclasses = list()  # type: List[RegClass]
         self.legalize_codes = OrderedDict()  # type: OrderedDict[XFormGroup, int]  # noqa
 
+        assert InstructionGroup._current is None,\
+            "InstructionGroup {} is still open!"\
+            .format(InstructionGroup._current.name)
+
     def __str__(self):
         # type: () -> str
         return self.name
diff --git a/lib/cretonne/meta/isa/intel/instructions.py b/lib/cretonne/meta/isa/intel/instructions.py
index a5c2bdafb0..c9d87c43f3 100644
--- a/lib/cretonne/meta/isa/intel/instructions.py
+++ b/lib/cretonne/meta/isa/intel/instructions.py
@@ -43,3 +43,5 @@ sdivmodx = Instruction(
         Return both quotient and remainder.
         """,
         ins=(nlo, nhi, d), outs=(q, r), can_trap=True)
+
+GROUP.close()