riscv64: Implement fcmp in ISLE (#5512)

Rework the compilation of fcmp in the riscv64 backend to be in ISLE, removing the need for the dedicated Fcmp instruction. This change is motivated by #5500, which showed that the riscv64 backend was generating branch instructions in the middle of a basic block.

We can't remove lower_br_fcmp quite yet as it's used in a few places in the emit module, but it's now no longer reachable from the ISLE lowerings.

Fixes #5500

cranelift/codegen/src/isa/riscv64/lower/isle.rs

@@ -61,28 +61,6 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
         }
     }
 
-    fn lower_br_fcmp(
-        &mut self,
-        cc: &FloatCC,
-        a: Reg,
-        b: Reg,
-        targets: &VecMachLabel,
-        ty: Type,
-    ) -> Unit {
-        let tmp = self.temp_writable_reg(I64);
-        MInst::lower_br_fcmp(
-            *cc,
-            a,
-            b,
-            BranchTarget::Label(targets[0]),
-            BranchTarget::Label(targets[1]),
-            ty,
-            tmp,
-        )
-        .iter()
-        .for_each(|i| self.emit(i));
-    }
-
     fn lower_brz_or_nz(
         &mut self,
         cc: &IntCC,
@@ -434,6 +412,15 @@ impl generated_code::Context for IsleContext<'_, '_, MInst, Riscv64Backend> {
 
         tmp.to_reg()
     }
+
+    #[inline]
+    fn int_compare(&mut self, kind: &IntCC, rs1: Reg, rs2: Reg) -> IntegerCompare {
+        IntegerCompare {
+            kind: *kind,
+            rs1,
+            rs2,
+        }
+    }
 }
 
 impl IsleContext<'_, '_, MInst, Riscv64Backend> {