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machinst x64: expand encoding names a bit;

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This avoids one, two, and three letter structures names, which makes the
code easier to read (while a bit more verbose).
This commit is contained in:
Benjamin Bouvier
2020-06-11 15:09:45 +02:00
parent ef5de04d32
commit b2a0718404
6 changed files with 607 additions and 369 deletions
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20
cranelift/codegen/src/isa/x64/lower.rs
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@@ -145,12 +145,12 @@ fn lower_insn_to_regs<'a>(ctx: Ctx<'a>, iri: IRInst) {
let regR = input_to_reg(ctx, iri, 1);
let is64 = int_ty_is_64(ty.unwrap());
let how = if op == Opcode::Iadd {
RMI_R_Op::Add
AluRmiROpcode::Add
} else {
RMI_R_Op::Sub
AluRmiROpcode::Sub
};
ctx.emit(Inst::mov_r_r(true, regL, regD));
ctx.emit(Inst::alu_rmi_r(is64, how, RMI::reg(regR), regD));
ctx.emit(Inst::alu_rmi_r(is64, how, RegMemImm::reg(regR), regD));
}
Opcode::Ishl | Opcode::Ushr | Opcode::Sshr => {
@@ -205,7 +205,7 @@ fn lower_insn_to_regs<'a>(ctx: Ctx<'a>, iri: IRInst) {
if src_reg.get_class() == RegClass::I64 {
ctx.emit(Inst::mov_r_r(true, src_reg, retval_reg));
} else if src_reg.get_class() == RegClass::V128 {
ctx.emit(Inst::xmm_r_r(SSE_Op::SSE2_Movsd, src_reg, retval_reg));
ctx.emit(Inst::xmm_r_r(SseOpcode::Movsd, src_reg, retval_reg));
}
}
// N.B.: the Ret itself is generated by the ABI.
@@ -247,12 +247,12 @@ fn lower_insn_to_regs<'a>(ctx: Ctx<'a>, iri: IRInst) {
let is64 = flt_ty_is_64(ty.unwrap());
if !is64 {
let inst = if op == Opcode::Fadd {
SSE_Op::SSE_Addss
SseOpcode::Addss
} else {
SSE_Op::SSE_Subss
SseOpcode::Subss
};
ctx.emit(Inst::xmm_r_r(SSE_Op::SSE_Movss, regL, regD));
ctx.emit(Inst::xmm_rm_r(inst, RM::reg(regR), regD));
ctx.emit(Inst::xmm_r_r(SseOpcode::Movss, regL, regD));
ctx.emit(Inst::xmm_rm_r(inst, RegMem::reg(regR), regD));
} else {
unimplemented!("unimplemented lowering for opcode {:?}", op);
}
@@ -317,7 +317,7 @@ impl LowerBackend for X64Backend {
_ => unreachable!(),
};
let sizeB = int_ty_to_sizeB(tyS);
ctx.emit(Inst::cmp_rmi_r(sizeB, RMI::imm(0), rS));
ctx.emit(Inst::cmp_rmi_r(sizeB, RegMemImm::imm(0), rS));
ctx.emit(Inst::jmp_cond_symm(cc, taken, not_taken));
} else {
unimplemented = true;
@@ -331,7 +331,7 @@ impl LowerBackend for X64Backend {
let cc = intCC_to_x64_CC(inst_condcode(ctx.data(branches[0])));
let sizeB = int_ty_to_sizeB(tyS);
// FIXME verify rSR vs rSL ordering
ctx.emit(Inst::cmp_rmi_r(sizeB, RMI::reg(rSR), rSL));
ctx.emit(Inst::cmp_rmi_r(sizeB, RegMemImm::reg(rSR), rSL));
ctx.emit(Inst::jmp_cond_symm(cc, taken, not_taken));
} else {
unimplemented = true;