diff --git a/cranelift/codegen/src/isa/x64/lower.rs b/cranelift/codegen/src/isa/x64/lower.rs
index 39d6f9fb57..0b9784d59d 100644
--- a/cranelift/codegen/src/isa/x64/lower.rs
+++ b/cranelift/codegen/src/isa/x64/lower.rs
@@ -4107,7 +4107,7 @@ fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
             //     unused load.
             let src = input_to_reg_mem(ctx, inputs[0]);
             let src_ty = ctx.input_ty(insn, 0);
-            let dst = get_output_reg(ctx, outputs[0]);
+            let dst = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
             let dst_ty = ty.unwrap();
             assert!(src_ty == dst_ty.lane_type() && dst_ty.bits() == 128);
             match src {