From b24c561cebf05b365cb70d722ce845273a61d5d0 Mon Sep 17 00:00:00 2001
From: Nick Fitzgerald <fitzgen@gmail.com>
Date: Thu, 21 Jul 2022 15:31:05 -0700
Subject: [PATCH] cranelift: Don't log CLIF and assembly at debug level (#4503)

Too verbose. Only log them at trace level.
---
 cranelift/codegen/src/context.rs     | 2 +-
 cranelift/codegen/src/isa/x64/mod.rs | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/cranelift/codegen/src/context.rs b/cranelift/codegen/src/context.rs
index 9216de8d1d..5cc50f5c54 100644
--- a/cranelift/codegen/src/context.rs
+++ b/cranelift/codegen/src/context.rs
@@ -133,7 +133,7 @@ impl Context {
         self.verify_if(isa)?;
 
         let opt_level = isa.flags().opt_level();
-        log::debug!(
+        log::trace!(
             "Compiling (opt level {:?}):\n{}",
             opt_level,
             self.func.display()
diff --git a/cranelift/codegen/src/isa/x64/mod.rs b/cranelift/codegen/src/isa/x64/mod.rs
index cb03b558d9..c8b704ac23 100644
--- a/cranelift/codegen/src/isa/x64/mod.rs
+++ b/cranelift/codegen/src/isa/x64/mod.rs
@@ -76,7 +76,7 @@ impl TargetIsa for X64Backend {
         let dynamic_stackslot_offsets = emit_result.dynamic_stackslot_offsets;
 
         if let Some(disasm) = emit_result.disasm.as_ref() {
-            log::debug!("disassembly:\n{}", disasm);
+            log::trace!("disassembly:\n{}", disasm);
         }
 
         Ok(MachCompileResult {