From fa63e7de5ad588fcd77db6690ec476dbd63b764c Mon Sep 17 00:00:00 2001 From: Alex Crichton Date: Fri, 19 Nov 2021 07:19:21 -0800 Subject: [PATCH] aarch64: Migrate `ineg` to ISLE Needed a new `vec_misc` instruction construction helper but otherwise a pretty straightforward translation. --- cranelift/codegen/src/isa/aarch64/inst.isle | 7 + cranelift/codegen/src/isa/aarch64/lower.isle | 10 + .../lower/isle/generated_code.manifest | 4 +- .../isa/aarch64/lower/isle/generated_code.rs | 816 ++++++++++-------- .../codegen/src/isa/aarch64/lower_inst.rs | 19 +- 5 files changed, 473 insertions(+), 383 deletions(-) diff --git a/cranelift/codegen/src/isa/aarch64/inst.isle b/cranelift/codegen/src/isa/aarch64/inst.isle index 704895ab01..ba99c03b10 100644 --- a/cranelift/codegen/src/isa/aarch64/inst.isle +++ b/cranelift/codegen/src/isa/aarch64/inst.isle @@ -1448,6 +1448,13 @@ (ConsumesFlags.ConsumesFlags (MInst.AluRRR (ALUOp.Sbc64) dst src1 src2) (writable_reg_to_reg dst)))) +;; Helper for emitting `MInst.VecMisc` instructions. +(decl vec_misc (VecMisc2 Reg VectorSize) Reg) +(rule (vec_misc op src size) + (let ((dst WritableReg (temp_writable_reg $I8X16)) + (_ Unit (emit (MInst.VecMisc op dst src size)))) + (writable_reg_to_reg dst))) + ;; Immediate value helpers ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; (decl imm (Type u64) Reg) diff --git a/cranelift/codegen/src/isa/aarch64/lower.isle b/cranelift/codegen/src/isa/aarch64/lower.isle index df8713a02a..de548231b1 100644 --- a/cranelift/codegen/src/isa/aarch64/lower.isle +++ b/cranelift/codegen/src/isa/aarch64/lower.isle @@ -179,3 +179,13 @@ (rule (lower (has_type (vec128 ty) (ssub_sat x y))) (value_reg (vec_rrr (VecALUOp.Sqsub) (put_in_reg x) (put_in_reg y) (vector_size ty)))) + +;;;; Rules for `ineg` ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +;; `i64` and smaller. +(rule (lower (has_type (fits_in_64 ty) (ineg x))) + (value_reg (alu_rrr (isub_op ty) (zero_reg) (put_in_reg x)))) + +;; vectors. +(rule (lower (has_type (vec128 ty) (ineg x))) + (value_reg (vec_misc (VecMisc2.Neg) (put_in_reg x) (vector_size ty)))) diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest index 7452e9507e..c976fb5a4b 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.manifest @@ -1,4 +1,4 @@ src/clif.isle 9c0563583e5500de00ec5e226edc0547ac3ea789c8d76f1da0401c80ec619320fdc9a6f17fd76bbcac74a5894f85385c1f51c900c2b83bc9906d03d0f29bf5cb src/prelude.isle e4933f2bcb6cd9e00cb6dc0c47c43d096d0c4e37468af17a38fad8906b864d975e0a8b98d15c6a5e2bccf255ec2ced2466991c3405533e9cafefbf4d9ac46823 -src/isa/aarch64/inst.isle 67a43022bb2e0b8ae06b71c7c49f9b9997a9c6ca109e35f5018b9cd64105a0fe8b103943fb34ca7da45cea9db7327e00954e88606845d5ebc370bc6c3045a04f -src/isa/aarch64/lower.isle f3699bd266aa0fe5389ace7d4e6e79b7f8778e61cd803b564af8508541b8e3c3235431a3bb83bbec46cdbc92236fd84b0ad290a276ff34d24129a8b3aa54ad0d +src/isa/aarch64/inst.isle c90a42ae8e0d932d200c6150777fa6a8b6d113f2e9ef24a9328669d9d9bebf137004e70eaef91b9be1880eb71e5b1cb28f84d53e2a11c0c45db3c57f5c32441e +src/isa/aarch64/lower.isle 5b9b2423ff641cb9bc3b297a0fba87813421200de7b83c8d575e52e643439971fb912be8d41043ecbe65107678451a74dfec0012df13dfca34bbfed4857504af diff --git a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs index 04209b4573..816306b477 100644 --- a/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs +++ b/cranelift/codegen/src/isa/aarch64/lower/isle/generated_code.rs @@ -1428,31 +1428,55 @@ pub fn constructor_sbc64(ctx: &mut C, arg0: Reg, arg1: Reg) -> Optio return Some(expr5_0); } +// Generated as internal constructor for term vec_misc. +pub fn constructor_vec_misc( + ctx: &mut C, + arg0: &VecMisc2, + arg1: Reg, + arg2: &VectorSize, +) -> Option { + let pattern0_0 = arg0; + let pattern1_0 = arg1; + let pattern2_0 = arg2; + // Rule at src/isa/aarch64/inst.isle line 1453. + let expr0_0: Type = I8X16; + let expr1_0 = C::temp_writable_reg(ctx, expr0_0); + let expr2_0 = MInst::VecMisc { + op: pattern0_0.clone(), + rd: expr1_0, + rn: pattern1_0, + size: pattern2_0.clone(), + }; + let expr3_0 = C::emit(ctx, &expr2_0); + let expr4_0 = C::writable_reg_to_reg(ctx, expr1_0); + return Some(expr4_0); +} + // Generated as internal constructor for term imm. pub fn constructor_imm(ctx: &mut C, arg0: Type, arg1: u64) -> Option { let pattern0_0 = arg0; if let Some(pattern1_0) = C::integral_ty(ctx, pattern0_0) { let pattern2_0 = arg1; if let Some(pattern3_0) = C::imm_logic_from_u64(ctx, pattern2_0) { - // Rule at src/isa/aarch64/inst.isle line 1464. + // Rule at src/isa/aarch64/inst.isle line 1471. let expr0_0 = ALUOp::Orr64; let expr1_0 = C::zero_reg(ctx); let expr2_0 = constructor_alu_rr_imm_logic(ctx, &expr0_0, expr1_0, pattern3_0)?; return Some(expr2_0); } if let Some(pattern3_0) = C::move_wide_const_from_u64(ctx, pattern2_0) { - // Rule at src/isa/aarch64/inst.isle line 1456. + // Rule at src/isa/aarch64/inst.isle line 1463. let expr0_0 = OperandSize::Size64; let expr1_0 = constructor_movz(ctx, pattern3_0, &expr0_0)?; return Some(expr1_0); } if let Some(pattern3_0) = C::move_wide_const_from_negated_u64(ctx, pattern2_0) { - // Rule at src/isa/aarch64/inst.isle line 1460. + // Rule at src/isa/aarch64/inst.isle line 1467. let expr0_0 = OperandSize::Size64; let expr1_0 = constructor_movn(ctx, pattern3_0, &expr0_0)?; return Some(expr1_0); } - // Rule at src/isa/aarch64/inst.isle line 1471. + // Rule at src/isa/aarch64/inst.isle line 1478. let expr0_0 = C::load_constant64_full(ctx, pattern2_0); return Some(expr0_0); } @@ -1598,198 +1622,340 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option { - let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) { - let pattern9_0 = C::inst_data(ctx, pattern8_0); - match &pattern9_0 { - &InstructionData::UnaryImm { - opcode: ref pattern10_0, - imm: pattern10_1, - } => { - if let &Opcode::Iconst = &pattern10_0 { - let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); - if let Some(pattern13_0) = - C::imm12_from_u64(ctx, pattern12_0) - { - // Rule at src/isa/aarch64/lower.isle line 37. - let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_1); - let expr2_0 = constructor_alu_rr_imm12( - ctx, - &expr0_0, - expr1_0, - pattern13_0, - )?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - if let Some(pattern13_0) = - C::imm12_from_negated_u64(ctx, pattern12_0) - { - // Rule at src/isa/aarch64/lower.isle line 45. - let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_1); - let expr2_0 = constructor_alu_rr_imm12( - ctx, - &expr0_0, - expr1_0, - pattern13_0, - )?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); + match &pattern4_0 { + &InstructionData::Binary { + opcode: ref pattern5_0, + args: ref pattern5_1, + } => { + match &pattern5_0 { + &Opcode::Iadd => { + let (pattern7_0, pattern7_1) = + C::unpack_value_array_2(ctx, &pattern5_1); + if let Some(pattern8_0) = C::def_inst(ctx, pattern7_0) { + let pattern9_0 = C::inst_data(ctx, pattern8_0); + match &pattern9_0 { + &InstructionData::UnaryImm { + opcode: ref pattern10_0, + imm: pattern10_1, + } => { + if let &Opcode::Iconst = &pattern10_0 { + let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); + if let Some(pattern13_0) = + C::imm12_from_u64(ctx, pattern12_0) + { + // Rule at src/isa/aarch64/lower.isle line 37. + let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_1); + let expr2_0 = constructor_alu_rr_imm12( + ctx, + &expr0_0, + expr1_0, + pattern13_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } + if let Some(pattern13_0) = + C::imm12_from_negated_u64(ctx, pattern12_0) + { + // Rule at src/isa/aarch64/lower.isle line 45. + let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_1); + let expr2_0 = constructor_alu_rr_imm12( + ctx, + &expr0_0, + expr1_0, + pattern13_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } } } - } - &InstructionData::Binary { - opcode: ref pattern10_0, - args: ref pattern10_1, - } => { - match &pattern10_0 { - &Opcode::Imul => { - let (pattern12_0, pattern12_1) = - C::unpack_value_array_2(ctx, &pattern10_1); - // Rule at src/isa/aarch64/lower.isle line 70. - let expr0_0 = constructor_madd_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern12_0); - let expr2_0 = C::put_in_reg(ctx, pattern12_1); - let expr3_0 = C::put_in_reg(ctx, pattern7_1); - let expr4_0 = constructor_alu_rrrr( - ctx, &expr0_0, expr1_0, expr2_0, expr3_0, - )?; - let expr5_0 = C::value_reg(ctx, expr4_0); - return Some(expr5_0); - } - &Opcode::Ishl => { - let (pattern12_0, pattern12_1) = - C::unpack_value_array_2(ctx, &pattern10_1); - if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1) - { - let pattern14_0 = C::inst_data(ctx, pattern13_0); - if let &InstructionData::UnaryImm { - opcode: ref pattern15_0, - imm: pattern15_1, - } = &pattern14_0 + &InstructionData::Binary { + opcode: ref pattern10_0, + args: ref pattern10_1, + } => { + match &pattern10_0 { + &Opcode::Imul => { + let (pattern12_0, pattern12_1) = + C::unpack_value_array_2(ctx, &pattern10_1); + // Rule at src/isa/aarch64/lower.isle line 70. + let expr0_0 = constructor_madd_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern12_0); + let expr2_0 = C::put_in_reg(ctx, pattern12_1); + let expr3_0 = C::put_in_reg(ctx, pattern7_1); + let expr4_0 = constructor_alu_rrrr( + ctx, &expr0_0, expr1_0, expr2_0, expr3_0, + )?; + let expr5_0 = C::value_reg(ctx, expr4_0); + return Some(expr5_0); + } + &Opcode::Ishl => { + let (pattern12_0, pattern12_1) = + C::unpack_value_array_2(ctx, &pattern10_1); + if let Some(pattern13_0) = + C::def_inst(ctx, pattern12_1) { - if let &Opcode::Iconst = &pattern15_0 { - let closure17 = || { - return Some(pattern3_0); - }; - if let Some(pattern17_0) = closure17() { - if let Some(pattern18_0) = - C::lshl_from_imm64( - ctx, - pattern15_1, - pattern17_0, - ) - { - // Rule at src/isa/aarch64/lower.isle line 62. - let expr0_0 = constructor_iadd_op( - ctx, pattern3_0, - )?; - let expr1_0 = - C::put_in_reg(ctx, pattern7_1); - let expr2_0 = - C::put_in_reg(ctx, pattern12_0); - let expr3_0 = - constructor_alu_rrr_shift( + let pattern14_0 = + C::inst_data(ctx, pattern13_0); + if let &InstructionData::UnaryImm { + opcode: ref pattern15_0, + imm: pattern15_1, + } = &pattern14_0 + { + if let &Opcode::Iconst = &pattern15_0 { + let closure17 = || { + return Some(pattern3_0); + }; + if let Some(pattern17_0) = closure17() { + if let Some(pattern18_0) = + C::lshl_from_imm64( ctx, - &expr0_0, - expr1_0, - expr2_0, - pattern18_0, - )?; - let expr4_0 = - C::value_reg(ctx, expr3_0); - return Some(expr4_0); + pattern15_1, + pattern17_0, + ) + { + // Rule at src/isa/aarch64/lower.isle line 62. + let expr0_0 = + constructor_iadd_op( + ctx, pattern3_0, + )?; + let expr1_0 = C::put_in_reg( + ctx, pattern7_1, + ); + let expr2_0 = C::put_in_reg( + ctx, + pattern12_0, + ); + let expr3_0 = + constructor_alu_rrr_shift( + ctx, + &expr0_0, + expr1_0, + expr2_0, + pattern18_0, + )?; + let expr4_0 = + C::value_reg(ctx, expr3_0); + return Some(expr4_0); + } } } } } } + _ => {} } - _ => {} } + _ => {} } - _ => {} } - } - if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0) { - // Rule at src/isa/aarch64/lower.isle line 53. - let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_1); - let expr2_0 = - constructor_alu_rr_extend_reg(ctx, &expr0_0, expr1_0, &pattern8_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { - let pattern9_0 = C::inst_data(ctx, pattern8_0); - match &pattern9_0 { - &InstructionData::UnaryImm { - opcode: ref pattern10_0, - imm: pattern10_1, - } => { - if let &Opcode::Iconst = &pattern10_0 { - let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); - if let Some(pattern13_0) = - C::imm12_from_u64(ctx, pattern12_0) - { - // Rule at src/isa/aarch64/lower.isle line 34. - let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = constructor_alu_rr_imm12( - ctx, - &expr0_0, - expr1_0, - pattern13_0, - )?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - if let Some(pattern13_0) = - C::imm12_from_negated_u64(ctx, pattern12_0) - { - // Rule at src/isa/aarch64/lower.isle line 42. - let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = constructor_alu_rr_imm12( - ctx, - &expr0_0, - expr1_0, - pattern13_0, - )?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); + if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_0) + { + // Rule at src/isa/aarch64/lower.isle line 53. + let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_1); + let expr2_0 = constructor_alu_rr_extend_reg( + ctx, + &expr0_0, + expr1_0, + &pattern8_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } + if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { + let pattern9_0 = C::inst_data(ctx, pattern8_0); + match &pattern9_0 { + &InstructionData::UnaryImm { + opcode: ref pattern10_0, + imm: pattern10_1, + } => { + if let &Opcode::Iconst = &pattern10_0 { + let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); + if let Some(pattern13_0) = + C::imm12_from_u64(ctx, pattern12_0) + { + // Rule at src/isa/aarch64/lower.isle line 34. + let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = constructor_alu_rr_imm12( + ctx, + &expr0_0, + expr1_0, + pattern13_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } + if let Some(pattern13_0) = + C::imm12_from_negated_u64(ctx, pattern12_0) + { + // Rule at src/isa/aarch64/lower.isle line 42. + let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = constructor_alu_rr_imm12( + ctx, + &expr0_0, + expr1_0, + pattern13_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } } } - } - &InstructionData::Binary { - opcode: ref pattern10_0, - args: ref pattern10_1, - } => { - match &pattern10_0 { - &Opcode::Imul => { - let (pattern12_0, pattern12_1) = - C::unpack_value_array_2(ctx, &pattern10_1); - // Rule at src/isa/aarch64/lower.isle line 67. - let expr0_0 = constructor_madd_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern12_0); - let expr2_0 = C::put_in_reg(ctx, pattern12_1); - let expr3_0 = C::put_in_reg(ctx, pattern7_0); - let expr4_0 = constructor_alu_rrrr( - ctx, &expr0_0, expr1_0, expr2_0, expr3_0, - )?; - let expr5_0 = C::value_reg(ctx, expr4_0); - return Some(expr5_0); + &InstructionData::Binary { + opcode: ref pattern10_0, + args: ref pattern10_1, + } => { + match &pattern10_0 { + &Opcode::Imul => { + let (pattern12_0, pattern12_1) = + C::unpack_value_array_2(ctx, &pattern10_1); + // Rule at src/isa/aarch64/lower.isle line 67. + let expr0_0 = constructor_madd_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern12_0); + let expr2_0 = C::put_in_reg(ctx, pattern12_1); + let expr3_0 = C::put_in_reg(ctx, pattern7_0); + let expr4_0 = constructor_alu_rrrr( + ctx, &expr0_0, expr1_0, expr2_0, expr3_0, + )?; + let expr5_0 = C::value_reg(ctx, expr4_0); + return Some(expr5_0); + } + &Opcode::Ishl => { + let (pattern12_0, pattern12_1) = + C::unpack_value_array_2(ctx, &pattern10_1); + if let Some(pattern13_0) = + C::def_inst(ctx, pattern12_1) + { + let pattern14_0 = + C::inst_data(ctx, pattern13_0); + if let &InstructionData::UnaryImm { + opcode: ref pattern15_0, + imm: pattern15_1, + } = &pattern14_0 + { + if let &Opcode::Iconst = &pattern15_0 { + let closure17 = || { + return Some(pattern3_0); + }; + if let Some(pattern17_0) = closure17() { + if let Some(pattern18_0) = + C::lshl_from_imm64( + ctx, + pattern15_1, + pattern17_0, + ) + { + // Rule at src/isa/aarch64/lower.isle line 58. + let expr0_0 = + constructor_iadd_op( + ctx, pattern3_0, + )?; + let expr1_0 = C::put_in_reg( + ctx, pattern7_0, + ); + let expr2_0 = C::put_in_reg( + ctx, + pattern12_0, + ); + let expr3_0 = + constructor_alu_rrr_shift( + ctx, + &expr0_0, + expr1_0, + expr2_0, + pattern18_0, + )?; + let expr4_0 = + C::value_reg(ctx, expr3_0); + return Some(expr4_0); + } + } + } + } + } + } + _ => {} } - &Opcode::Ishl => { + } + _ => {} + } + } + if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1) + { + // Rule at src/isa/aarch64/lower.isle line 50. + let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = constructor_alu_rr_extend_reg( + ctx, + &expr0_0, + expr1_0, + &pattern8_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } + // Rule at src/isa/aarch64/lower.isle line 30. + let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = C::put_in_reg(ctx, pattern7_1); + let expr3_0 = constructor_alu_rrr(ctx, &expr0_0, expr1_0, expr2_0)?; + let expr4_0 = C::value_reg(ctx, expr3_0); + return Some(expr4_0); + } + &Opcode::Isub => { + let (pattern7_0, pattern7_1) = + C::unpack_value_array_2(ctx, &pattern5_1); + if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { + let pattern9_0 = C::inst_data(ctx, pattern8_0); + match &pattern9_0 { + &InstructionData::UnaryImm { + opcode: ref pattern10_0, + imm: pattern10_1, + } => { + if let &Opcode::Iconst = &pattern10_0 { + let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); + if let Some(pattern13_0) = + C::imm12_from_u64(ctx, pattern12_0) + { + // Rule at src/isa/aarch64/lower.isle line 121. + let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = constructor_alu_rr_imm12( + ctx, + &expr0_0, + expr1_0, + pattern13_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } + if let Some(pattern13_0) = + C::imm12_from_negated_u64(ctx, pattern12_0) + { + // Rule at src/isa/aarch64/lower.isle line 126. + let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = constructor_alu_rr_imm12( + ctx, + &expr0_0, + expr1_0, + pattern13_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); + } + } + } + &InstructionData::Binary { + opcode: ref pattern10_0, + args: ref pattern10_1, + } => { + if let &Opcode::Ishl = &pattern10_0 { let (pattern12_0, pattern12_1) = C::unpack_value_array_2(ctx, &pattern10_1); if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1) @@ -1812,8 +1978,8 @@ pub fn constructor_lower(ctx: &mut C, arg0: Inst) -> Option(ctx: &mut C, arg0: Inst) -> Option {} } + _ => {} } - _ => {} } - } - if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1) { - // Rule at src/isa/aarch64/lower.isle line 50. - let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = - constructor_alu_rr_extend_reg(ctx, &expr0_0, expr1_0, &pattern8_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - // Rule at src/isa/aarch64/lower.isle line 30. - let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = C::put_in_reg(ctx, pattern7_1); - let expr3_0 = constructor_alu_rrr(ctx, &expr0_0, expr1_0, expr2_0)?; - let expr4_0 = C::value_reg(ctx, expr3_0); - return Some(expr4_0); - } - &Opcode::Isub => { - let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - if let Some(pattern8_0) = C::def_inst(ctx, pattern7_1) { - let pattern9_0 = C::inst_data(ctx, pattern8_0); - match &pattern9_0 { - &InstructionData::UnaryImm { - opcode: ref pattern10_0, - imm: pattern10_1, - } => { - if let &Opcode::Iconst = &pattern10_0 { - let pattern12_0 = C::u64_from_imm64(ctx, pattern10_1); - if let Some(pattern13_0) = - C::imm12_from_u64(ctx, pattern12_0) - { - // Rule at src/isa/aarch64/lower.isle line 121. - let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = constructor_alu_rr_imm12( - ctx, - &expr0_0, - expr1_0, - pattern13_0, - )?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - if let Some(pattern13_0) = - C::imm12_from_negated_u64(ctx, pattern12_0) - { - // Rule at src/isa/aarch64/lower.isle line 126. - let expr0_0 = constructor_iadd_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = constructor_alu_rr_imm12( - ctx, - &expr0_0, - expr1_0, - pattern13_0, - )?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); - } - } - } - &InstructionData::Binary { - opcode: ref pattern10_0, - args: ref pattern10_1, - } => { - if let &Opcode::Ishl = &pattern10_0 { - let (pattern12_0, pattern12_1) = - C::unpack_value_array_2(ctx, &pattern10_1); - if let Some(pattern13_0) = C::def_inst(ctx, pattern12_1) { - let pattern14_0 = C::inst_data(ctx, pattern13_0); - if let &InstructionData::UnaryImm { - opcode: ref pattern15_0, - imm: pattern15_1, - } = &pattern14_0 - { - if let &Opcode::Iconst = &pattern15_0 { - let closure17 = || { - return Some(pattern3_0); - }; - if let Some(pattern17_0) = closure17() { - if let Some(pattern18_0) = - C::lshl_from_imm64( - ctx, - pattern15_1, - pattern17_0, - ) - { - // Rule at src/isa/aarch64/lower.isle line 136. - let expr0_0 = constructor_isub_op( - ctx, pattern3_0, - )?; - let expr1_0 = - C::put_in_reg(ctx, pattern7_0); - let expr2_0 = - C::put_in_reg(ctx, pattern12_0); - let expr3_0 = - constructor_alu_rrr_shift( - ctx, - &expr0_0, - expr1_0, - expr2_0, - pattern18_0, - )?; - let expr4_0 = - C::value_reg(ctx, expr3_0); - return Some(expr4_0); - } - } - } - } - } - } - } - _ => {} + if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1) + { + // Rule at src/isa/aarch64/lower.isle line 131. + let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = constructor_alu_rr_extend_reg( + ctx, + &expr0_0, + expr1_0, + &pattern8_0, + )?; + let expr3_0 = C::value_reg(ctx, expr2_0); + return Some(expr3_0); } - } - if let Some(pattern8_0) = C::extended_value_from_value(ctx, pattern7_1) { - // Rule at src/isa/aarch64/lower.isle line 131. + // Rule at src/isa/aarch64/lower.isle line 117. let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = - constructor_alu_rr_extend_reg(ctx, &expr0_0, expr1_0, &pattern8_0)?; - let expr3_0 = C::value_reg(ctx, expr2_0); - return Some(expr3_0); + let expr2_0 = C::put_in_reg(ctx, pattern7_1); + let expr3_0 = constructor_alu_rrr(ctx, &expr0_0, expr1_0, expr2_0)?; + let expr4_0 = C::value_reg(ctx, expr3_0); + return Some(expr4_0); } - // Rule at src/isa/aarch64/lower.isle line 117. + _ => {} + } + } + &InstructionData::Unary { + opcode: ref pattern5_0, + arg: pattern5_1, + } => { + if let &Opcode::Ineg = &pattern5_0 { + // Rule at src/isa/aarch64/lower.isle line 186. let expr0_0 = constructor_isub_op(ctx, pattern3_0)?; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = C::put_in_reg(ctx, pattern7_1); + let expr1_0 = C::zero_reg(ctx); + let expr2_0 = C::put_in_reg(ctx, pattern5_1); let expr3_0 = constructor_alu_rrr(ctx, &expr0_0, expr1_0, expr2_0)?; let expr4_0 = C::value_reg(ctx, expr3_0); return Some(expr4_0); } - _ => {} } + _ => {} } } if let Some(pattern3_0) = C::vec128(ctx, pattern2_0) { let pattern4_0 = C::inst_data(ctx, pattern0_0); - if let &InstructionData::Binary { - opcode: ref pattern5_0, - args: ref pattern5_1, - } = &pattern4_0 - { - match &pattern5_0 { - &Opcode::UaddSat => { - let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/aarch64/lower.isle line 165. - let expr0_0 = VecALUOp::Uqadd; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = C::put_in_reg(ctx, pattern7_1); - let expr3_0 = constructor_vector_size(ctx, pattern3_0)?; - let expr4_0 = - constructor_vec_rrr(ctx, &expr0_0, expr1_0, expr2_0, &expr3_0)?; - let expr5_0 = C::value_reg(ctx, expr4_0); - return Some(expr5_0); + match &pattern4_0 { + &InstructionData::Binary { + opcode: ref pattern5_0, + args: ref pattern5_1, + } => { + match &pattern5_0 { + &Opcode::UaddSat => { + let (pattern7_0, pattern7_1) = + C::unpack_value_array_2(ctx, &pattern5_1); + // Rule at src/isa/aarch64/lower.isle line 165. + let expr0_0 = VecALUOp::Uqadd; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = C::put_in_reg(ctx, pattern7_1); + let expr3_0 = constructor_vector_size(ctx, pattern3_0)?; + let expr4_0 = + constructor_vec_rrr(ctx, &expr0_0, expr1_0, expr2_0, &expr3_0)?; + let expr5_0 = C::value_reg(ctx, expr4_0); + return Some(expr5_0); + } + &Opcode::SaddSat => { + let (pattern7_0, pattern7_1) = + C::unpack_value_array_2(ctx, &pattern5_1); + // Rule at src/isa/aarch64/lower.isle line 170. + let expr0_0 = VecALUOp::Sqadd; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = C::put_in_reg(ctx, pattern7_1); + let expr3_0 = constructor_vector_size(ctx, pattern3_0)?; + let expr4_0 = + constructor_vec_rrr(ctx, &expr0_0, expr1_0, expr2_0, &expr3_0)?; + let expr5_0 = C::value_reg(ctx, expr4_0); + return Some(expr5_0); + } + &Opcode::UsubSat => { + let (pattern7_0, pattern7_1) = + C::unpack_value_array_2(ctx, &pattern5_1); + // Rule at src/isa/aarch64/lower.isle line 175. + let expr0_0 = VecALUOp::Uqsub; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = C::put_in_reg(ctx, pattern7_1); + let expr3_0 = constructor_vector_size(ctx, pattern3_0)?; + let expr4_0 = + constructor_vec_rrr(ctx, &expr0_0, expr1_0, expr2_0, &expr3_0)?; + let expr5_0 = C::value_reg(ctx, expr4_0); + return Some(expr5_0); + } + &Opcode::SsubSat => { + let (pattern7_0, pattern7_1) = + C::unpack_value_array_2(ctx, &pattern5_1); + // Rule at src/isa/aarch64/lower.isle line 180. + let expr0_0 = VecALUOp::Sqsub; + let expr1_0 = C::put_in_reg(ctx, pattern7_0); + let expr2_0 = C::put_in_reg(ctx, pattern7_1); + let expr3_0 = constructor_vector_size(ctx, pattern3_0)?; + let expr4_0 = + constructor_vec_rrr(ctx, &expr0_0, expr1_0, expr2_0, &expr3_0)?; + let expr5_0 = C::value_reg(ctx, expr4_0); + return Some(expr5_0); + } + _ => {} } - &Opcode::SaddSat => { - let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/aarch64/lower.isle line 170. - let expr0_0 = VecALUOp::Sqadd; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = C::put_in_reg(ctx, pattern7_1); - let expr3_0 = constructor_vector_size(ctx, pattern3_0)?; - let expr4_0 = - constructor_vec_rrr(ctx, &expr0_0, expr1_0, expr2_0, &expr3_0)?; - let expr5_0 = C::value_reg(ctx, expr4_0); - return Some(expr5_0); - } - &Opcode::UsubSat => { - let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/aarch64/lower.isle line 175. - let expr0_0 = VecALUOp::Uqsub; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = C::put_in_reg(ctx, pattern7_1); - let expr3_0 = constructor_vector_size(ctx, pattern3_0)?; - let expr4_0 = - constructor_vec_rrr(ctx, &expr0_0, expr1_0, expr2_0, &expr3_0)?; - let expr5_0 = C::value_reg(ctx, expr4_0); - return Some(expr5_0); - } - &Opcode::SsubSat => { - let (pattern7_0, pattern7_1) = C::unpack_value_array_2(ctx, &pattern5_1); - // Rule at src/isa/aarch64/lower.isle line 180. - let expr0_0 = VecALUOp::Sqsub; - let expr1_0 = C::put_in_reg(ctx, pattern7_0); - let expr2_0 = C::put_in_reg(ctx, pattern7_1); - let expr3_0 = constructor_vector_size(ctx, pattern3_0)?; - let expr4_0 = - constructor_vec_rrr(ctx, &expr0_0, expr1_0, expr2_0, &expr3_0)?; - let expr5_0 = C::value_reg(ctx, expr4_0); - return Some(expr5_0); - } - _ => {} } + &InstructionData::Unary { + opcode: ref pattern5_0, + arg: pattern5_1, + } => { + if let &Opcode::Ineg = &pattern5_0 { + // Rule at src/isa/aarch64/lower.isle line 190. + let expr0_0 = VecMisc2::Neg; + let expr1_0 = C::put_in_reg(ctx, pattern5_1); + let expr2_0 = constructor_vector_size(ctx, pattern3_0)?; + let expr3_0 = constructor_vec_misc(ctx, &expr0_0, expr1_0, &expr2_0)?; + let expr4_0 = C::value_reg(ctx, expr3_0); + return Some(expr4_0); + } + } + _ => {} } } } diff --git a/cranelift/codegen/src/isa/aarch64/lower_inst.rs b/cranelift/codegen/src/isa/aarch64/lower_inst.rs index f66b3275bf..396a9cf6d3 100644 --- a/cranelift/codegen/src/isa/aarch64/lower_inst.rs +++ b/cranelift/codegen/src/isa/aarch64/lower_inst.rs @@ -69,24 +69,7 @@ pub(crate) fn lower_insn_to_regs>( implemented_in_isle(ctx) } - Opcode::Ineg => { - let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap(); - let ty = ty.unwrap(); - if !ty.is_vector() { - let rn = zero_reg(); - let rm = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None); - let alu_op = choose_32_64(ty, ALUOp::Sub32, ALUOp::Sub64); - ctx.emit(Inst::AluRRR { alu_op, rd, rn, rm }); - } else { - let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None); - ctx.emit(Inst::VecMisc { - op: VecMisc2::Neg, - rd, - rn, - size: VectorSize::from_ty(ty), - }); - } - } + Opcode::Ineg => implemented_in_isle(ctx), Opcode::Imul => { let ty = ty.unwrap();