[s390x, abi_impl] Add i128 support (#4598)
This adds full i128 support to the s390x target, including new filetests and enabling the existing i128 runtest on s390x. The ABI requires that i128 is passed and returned via implicit pointer, but the front end still generates direct i128 types in call. This means we have to implement ABI support to implicitly convert i128 types to pointers when passing arguments. To do so, we add a new variant ABIArg::ImplicitArg. This acts like StructArg, except that the value type is the actual target type, not a pointer type. The required conversions have to be inserted in the prologue and at function call sites. Note that when dereferencing the implicit pointer in the prologue, we may require a temp register: the pointer may be passed on the stack so it needs to be loaded first, but the value register may be in the wrong class for pointer values. In this case, we use the "stack limit" register, which should be available at this point in the prologue. For return values, we use a mechanism similar to the one used for supporting multiple return values in the Wasmtime ABI. The only difference is that the hidden pointer to the return buffer must be the *first*, not last, argument in this case. (This implements the second half of issue #4565.)
This commit is contained in:
Ulrich Weigand
@@ -180,6 +180,8 @@ impl Inst {
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| Inst::VecIntCmpS { .. }
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| Inst::VecFloatCmp { .. }
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| Inst::VecFloatCmpS { .. }
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| Inst::VecInt128SCmpHi { .. }
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| Inst::VecInt128UCmpHi { .. }
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| Inst::VecLoad { .. }
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| Inst::VecStore { .. }
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| Inst::VecLoadReplicate { .. }
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@@ -394,6 +396,7 @@ impl Inst {
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lane_imm: 0,
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},
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_ if ty.is_vector() && ty.bits() == 128 => Inst::VecLoad { rd: into_reg, mem },
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types::B128 | types::I128 => Inst::VecLoad { rd: into_reg, mem },
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_ => unimplemented!("gen_load({})", ty),
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}
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}
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@@ -418,6 +421,7 @@ impl Inst {
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lane_imm: 0,
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},
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_ if ty.is_vector() && ty.bits() == 128 => Inst::VecStore { rd: from_reg, mem },
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types::B128 | types::I128 => Inst::VecStore { rd: from_reg, mem },
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_ => unimplemented!("gen_store({})", ty),
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}
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}
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@@ -736,6 +740,11 @@ fn s390x_get_operands<F: Fn(VReg) -> VReg>(inst: &Inst, collector: &mut OperandC
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collector.reg_use(rn);
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collector.reg_use(rm);
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}
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&Inst::VecInt128SCmpHi { tmp, rn, rm, .. } | &Inst::VecInt128UCmpHi { tmp, rn, rm, .. } => {
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collector.reg_def(tmp);
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collector.reg_use(rn);
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collector.reg_use(rm);
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}
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&Inst::VecLoad { rd, ref mem, .. } => {
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collector.reg_def(rd);
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memarg_operands(mem, collector);
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@@ -979,6 +988,11 @@ impl MachInst for Inst {
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.only_reg()
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.expect("multi-reg values not supported yet");
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match ty {
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types::I128 | types::B128 => {
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let mut ret = SmallVec::new();
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ret.push(Inst::load_vec_constant(to_reg, value));
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ret
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}
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_ if ty.is_vector() && ty.bits() == 128 => {
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let mut ret = SmallVec::new();
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ret.push(Inst::load_vec_constant(to_reg, value));
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@@ -1037,8 +1051,8 @@ impl MachInst for Inst {
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types::R64 => Ok((&[RegClass::Int], &[types::R64])),
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types::F32 => Ok((&[RegClass::Float], &[types::F32])),
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types::F64 => Ok((&[RegClass::Float], &[types::F64])),
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types::I128 => Ok((&[RegClass::Int, RegClass::Int], &[types::I64, types::I64])),
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types::B128 => Ok((&[RegClass::Int, RegClass::Int], &[types::B64, types::B64])),
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types::I128 => Ok((&[RegClass::Float], &[types::I128])),
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types::B128 => Ok((&[RegClass::Float], &[types::B128])),
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_ if ty.is_vector() && ty.bits() == 128 => Ok((&[RegClass::Float], &[types::I8X16])),
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// FIXME: We don't really have IFLAGS, but need to allow it here
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// for now to support the SelectifSpectreGuard instruction.
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@@ -2202,10 +2216,12 @@ impl Inst {
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VecBinaryOp::Add16x8 => "vah",
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VecBinaryOp::Add32x4 => "vaf",
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VecBinaryOp::Add64x2 => "vag",
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VecBinaryOp::Add128 => "vaq",
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VecBinaryOp::Sub8x16 => "vsb",
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VecBinaryOp::Sub16x8 => "vsh",
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VecBinaryOp::Sub32x4 => "vsf",
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VecBinaryOp::Sub64x2 => "vsg",
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VecBinaryOp::Sub128 => "vsq",
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VecBinaryOp::Mul8x16 => "vmlb",
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VecBinaryOp::Mul16x8 => "vmlhw",
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VecBinaryOp::Mul32x4 => "vmlf",
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@@ -2303,6 +2319,14 @@ impl Inst {
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VecUnaryOp::Popcnt16x8 => "vpopcth",
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VecUnaryOp::Popcnt32x4 => "vpopctf",
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VecUnaryOp::Popcnt64x2 => "vpopctg",
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VecUnaryOp::Clz8x16 => "vclzb",
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VecUnaryOp::Clz16x8 => "vclzh",
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VecUnaryOp::Clz32x4 => "vclzf",
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VecUnaryOp::Clz64x2 => "vclzg",
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VecUnaryOp::Ctz8x16 => "vctzb",
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VecUnaryOp::Ctz16x8 => "vctzh",
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VecUnaryOp::Ctz32x4 => "vctzf",
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VecUnaryOp::Ctz64x2 => "vctzg",
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VecUnaryOp::UnpackULow8x16 => "vupllb",
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VecUnaryOp::UnpackULow16x8 => "vupllh",
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VecUnaryOp::UnpackULow32x4 => "vupllf",
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@@ -2425,6 +2449,20 @@ impl Inst {
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let rm = pretty_print_reg(rm, allocs);
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format!("{}{} {}, {}, {}", op, s, rd, rn, rm)
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}
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&Inst::VecInt128SCmpHi { tmp, rn, rm } | &Inst::VecInt128UCmpHi { tmp, rn, rm } => {
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let op = match self {
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&Inst::VecInt128SCmpHi { .. } => "vecg",
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&Inst::VecInt128UCmpHi { .. } => "veclg",
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_ => unreachable!(),
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};
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let tmp = pretty_print_reg(tmp.to_reg(), allocs);
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let rn = pretty_print_reg(rn, allocs);
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let rm = pretty_print_reg(rm, allocs);
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format!(
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"{} {}, {} ; jne 10 ; vchlgs {}, {}, {}",
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op, rm, rn, tmp, rn, rm
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)
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}
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&Inst::VecLoad { rd, ref mem } | &Inst::VecLoadRev { rd, ref mem } => {
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let opcode = match self {
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&Inst::VecLoad { .. } => "vl",
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