From b0d414731c89e1ea28c0c4db78ba5bd0d600bb53 Mon Sep 17 00:00:00 2001 From: Dan Gohman Date: Mon, 9 Apr 2018 06:15:33 -0700 Subject: [PATCH] The addend for a PCRel4 reloc should be -4 too. --- cranelift/filetests/isa/intel/binary32.cton | 2 +- cranelift/filetests/isa/intel/binary64.cton | 2 +- lib/cretonne/meta/isa/intel/recipes.py | 4 +++- 3 files changed, 5 insertions(+), 3 deletions(-) diff --git a/cranelift/filetests/isa/intel/binary32.cton b/cranelift/filetests/isa/intel/binary32.cton index 2567fbe88c..c6bff52a64 100644 --- a/cranelift/filetests/isa/intel/binary32.cton +++ b/cranelift/filetests/isa/intel/binary32.cton @@ -352,7 +352,7 @@ ebb0: [-,%rsi] v351 = bint.i32 v301 ; bin: 0f b6 f2 ; asm: call foo - call fn0() ; bin: e8 PCRel4(%foo) 00000000 + call fn0() ; bin: e8 PCRel4(%foo-4) 00000000 ; asm: movl $0, %ecx [-,%rcx] v400 = func_addr.i32 fn0 ; bin: b9 Abs4(%foo) 00000000 diff --git a/cranelift/filetests/isa/intel/binary64.cton b/cranelift/filetests/isa/intel/binary64.cton index 1a47dc1cba..859c7d0d12 100644 --- a/cranelift/filetests/isa/intel/binary64.cton +++ b/cranelift/filetests/isa/intel/binary64.cton @@ -474,7 +474,7 @@ ebb0: [-,%rsi] v351 = bint.i64 v301 ; bin: 0f b6 f2 ; asm: call foo - call fn0() ; bin: e8 PCRel4(%foo) 00000000 + call fn0() ; bin: e8 PCRel4(%foo-4) 00000000 ; asm: movabsq $0, %rcx [-,%rcx] v400 = func_addr.i64 fn0 ; bin: 48 b9 Abs8(%foo) 0000000000000000 diff --git a/lib/cretonne/meta/isa/intel/recipes.py b/lib/cretonne/meta/isa/intel/recipes.py index 54df437c67..5f36e20291 100644 --- a/lib/cretonne/meta/isa/intel/recipes.py +++ b/lib/cretonne/meta/isa/intel/recipes.py @@ -1007,9 +1007,11 @@ call_id = TailRecipe( 'call_id', Call, size=4, ins=(), outs=(), emit=''' PUT_OP(bits, BASE_REX, sink); + // The addend adjusts for the difference between the end of the + // instruction and the beginning of the immediate field. sink.reloc_external(Reloc::IntelPCRel4, &func.dfg.ext_funcs[func_ref].name, - 0); + -4); sink.put4(0); ''')