Enable the simd_i8x16_arith2 test for AArch64

Copyright (c) 2021, Arm Limited.

build.rs

@@ -230,8 +230,7 @@ fn ignore(testsuite: &str, testname: &str, strategy: &str) -> bool {
             ("simd", _) if platform_is_s390x() => return true,
 
             // These are new instructions that are not really implemented in any backend.
-            ("simd", "simd_i8x16_arith2")
+            ("simd", "simd_conversions")
-            | ("simd", "simd_conversions")
             | ("simd", "simd_i16x8_extadd_pairwise_i8x16")
             | ("simd", "simd_i16x8_extmul_i8x16")
             | ("simd", "simd_i16x8_q15mulr_sat_s")

cranelift/codegen/src/isa/aarch64/lower_inst.rs

@@ -1181,9 +1181,29 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
         }
 
         Opcode::Popcnt => {
+            let ty = ty.unwrap();
+
+            if ty.is_vector() {
+                let lane_type = ty.lane_type();
+                let rd = get_output_reg(ctx, outputs[0]).only_reg().unwrap();
+                let rn = put_input_in_reg(ctx, inputs[0], NarrowValueMode::None);
+
+                if lane_type != I8 {
+                    return Err(CodegenError::Unsupported(format!(
+                        "Unsupported SIMD vector lane type: {:?}",
+                        lane_type
+                    )));
+                }
+
+                ctx.emit(Inst::VecMisc {
+                    op: VecMisc2::Cnt,
+                    rd,
+                    rn,
+                    size: VectorSize::from_ty(ty),
+                });
+            } else {
                 let out_regs = get_output_reg(ctx, outputs[0]);
                 let in_regs = put_input_in_regs(ctx, inputs[0]);
-            let ty = ty.unwrap();
                 let size = if ty == I128 {
                     ScalarSize::Size64
                 } else {
@@ -1259,10 +1279,12 @@ pub(crate) fn lower_insn_to_regs<C: LowerCtx<I = Inst>>(
                     idx: 0,
                     size: VectorSize::Size8x16,
                 });
+
                 if ty == I128 {
                     lower_constant_u64(ctx, out_regs.regs()[1], 0);
                 }
             }
+        }
 
         Opcode::Load
         | Opcode::Uload8